Methods and apparatus for configuring and reconfiguring a partial reconfiguration region

Patent metadata

Field	Value
Publication number	US-2016352338-A1
Application number	US-201615220216-A
Country	US
Kind code	A1
Filing date	Jul 26, 2016
Priority date	May 28, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a configuration shift register that includes a first partial reconfiguration region, a second partial reconfiguration region, a first multiplexer that receives signals from the first partial reconfiguration region, and a second multiplexer that receives signals from the second partial reconfiguration region; a first partial reconfiguration circuit that selectively enables the first partial reconfiguration region; and a second partial reconfiguration circuit that selectively enables the second partial reconfiguration region.

2 . The integrated circuit of claim 1 , wherein the first multiplexer is configured to selectively bypass the first partial reconfiguration region, and wherein the second multiplexer is configured to selectively bypass the second partial reconfiguration region.

3 . The integrated circuit of claim 1 , wherein the first multiplexer is controlled by the first partial reconfiguration circuit, and wherein the second multiplexer is controlled by the second partial reconfiguration circuit.

4 . The integrated circuit of claim 1 , wherein the first partial reconfiguration circuit includes a region control circuit.

5 . The integrated circuit of claim 4 , wherein the region control circuit includes a plurality of logic gates that receives global configuration control signals.

6 . The integrated circuit of claim 5 , further comprising:
an input-output block, wherein the first partial reconfiguration region receives signals from the plurality of logic gates, and wherein the input-output block receives signals from both the first partial reconfiguration region and the plurality of logic gates.

7 . The integrated circuit of claim 4 , wherein the first partial reconfiguration circuit further includes a region enable circuit that outputs signal to the region control circuit.

8 . The integrated circuit of claim 7 , wherein the region enable circuit includes an enable register and a shadow enable register that receives signals from the enable register.

9 . The integrated circuit of claim 7 , wherein the region enable circuit receives partial reconfiguration region enable control signals.

10 . The integrated circuit of claim 1 , wherein the first multiplexer is coupled between the first partial reconfiguration region and the second partial reconfiguration region.

11 . A method of operating an integrated circuit that includes a configuration shift register, the method comprising:
with a region control circuit, receiving global reconfiguration control signals and generating corresponding local reconfiguration control signals; and receiving the local reconfiguration control signals at the configuration shift register.

12 . The method of claim 11 , wherein the integrated circuit further includes core logic circuitry and input-output blocks, and wherein receiving the global reconfiguration control signals comprises receiving a global freeze signal that, when asserted, isolates the core logic circuitry from the input-output blocks.

13 . The method of claim 12 , wherein the global freeze signal is only asserted during a full configuration shift register configuration operation that reconfigures the entire configuration shift register.

14 . The method of claim 12 , wherein receiving the global reconfiguration control signals comprises receiving a done signal that indicates when reconfiguration of the configuration shift register is complete.

15 . The method of claim 12 , wherein receiving the global reconfiguration control signals comprises receiving a clock enable signal that, when asserted, allows data to be shifted into the configuration shift register.

16 . A method of operating an integrated circuit that includes a configuration shift register, comprising:
with a region enable circuit, receiving an asserted global freeze control signal; and in response to receiving the asserted global freeze control signal, asserting a corresponding local freeze control signal to a given partial reconfiguration region within the configuration shift register.

17 . The method of claim 16 , further comprising:
performing a partial reconfiguration operation on the given partial reconfiguration region while the global freeze control signal is deasserted.

18 . The method of claim 16 , further comprising:
with a region enable register, simultaneously receiving an asserted clock enable signal and an asserted enable data signal.

19 . The method of claim 18 , further comprising:
with the region enable register, generating a region enable output signal; and latching the region enable output signal at a shadow enable register that is connected in series with the region enable register.

20 . The method of claim 19 , further comprising:
asserting the local freeze control signal in response to determining that the shadow enable register has latched an asserted signal.

Assignees

• Altera Corp

Inventors

• Xiao Ping

Classifications

• H03K19/0008

  Arrangements for reducing power consumption · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• H03K19/17758

  for speeding up configuration or reconfiguration · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/17744

  for input/output signals · CPC title