Auto-referenced memory cell read techniques

Patent metadata

Field	Value
Publication number	US-2019198099-A1
Application number	US-201715853364-A
Country	US
Kind code	A1
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Jun 27, 2019
Grant date	—

Abstract

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

First claim

What is claimed is:

1 . A method, comprising:
initializing a counter in a controller coupled with a memory array; activating at least a portion of a first group of memory cells of the memory array by applying a read voltage to the memory array; determining that a set of memory cells has been activated based at least in part on applying the read voltage; updating the counter to a first value based at least in part on determining that the set of memory cells has been activated; comparing the first value of the updated counter to a threshold stored at the controller; and reading one or more memory cells of the memory array based at least in part on the comparison.

2 . The method of claim 1 , wherein the comparing further comprises:
determining that the first value satisfies the threshold stored at the controller; and stopping application of the read voltage to the memory array based at least in part on the determination that the first value satisfies the threshold, wherein the one or more memory cells are read after application of the read voltage has stopped.

3 . The method of claim 1 , wherein the comparing further comprises:
determining that the first value does not satisfy the threshold stored at the controller; maintaining application of the read voltage to the memory array based at least in part on the determination that the first value does not satisfy the threshold; determining that a second set of memory cells has been activated based at least in part on maintaining application of the read voltage; and updating the counter to a second value based at least in part on determining that the second set of memory cells has been activated, wherein the one or more memory cells are read based at least in part on updating the counter to the second value.

4 . The method of claim 1 , further comprising:
determining that the set of memory cells that has been activated corresponds to a first logic state.

5 . The method of claim 4 , wherein the first logic state corresponds to a first set of threshold voltages that is less than a second set of threshold voltages associated with a second logic state.

6 . The method of claim 1 , wherein the first group of memory cells are configured with a predetermined number of memory cells having a first logic state.

7 . The method of claim 1 , wherein the first group of memory cells are configured with a fixed number of memory cells independent of a total number of memory cells in the first group.

8 . The method of claim 1 , wherein a first half of the first group of memory cells corresponds to a first logic state and a second half of the first group of memory cells corresponds to a second logic state.

9 . The method of claim 1 , wherein each memory cell of the set of memory cells corresponds to a first logic state.

10 . The method of claim 1 , wherein the set of memory cells is half of the first group of memory cells.

11 . The method of claim 6 , wherein the threshold is equal to the predetermined number of memory cells having the first logic state.

12 . The method of claim 1 , wherein the threshold is read from a second group of memory cells of the memory array.

13 . The method of claim 1 , wherein the read voltage comprises a plurality of constant voltages each having a different value over a duration.

14 . A method, comprising:
receiving, at a controller, a first set of bits of an input vector from a host device; allocating a block of memory to store the first set of bits of the input vector and a second set of bits based at least in part on a total number bits of the first set of bits; generating the second set of bits based at least in part on a number of bits of the first set of bits having a first logic state; and writing the first set of bits and the second set of bits at the block of memory.

15 . The method of claim 14 , wherein:
the second set of bits comprises multiple couples of bits representative of the number of bits of the first set of bits having the first logic state.

16 . The method of claim 14 , wherein generating the second set of bits comprises:
determining the number of bits of the first set of bits having the first logic state; and generating a set of bit values corresponding to the determined number of bits.

17 . A method, comprising:
initializing a first counter and a second counter in a controller coupled with a memory array that comprises a first portion of memory cells and a second portion of memory cells; activating a first subset of the first portion of memory cells by applying a first read voltage to the memory array and a second subset of the second portion of memory cells by applying a second read voltage to the memory array; updating the first counter to a first value based at least in part on activating the first subset of memory cells and the second counter to a second value based at least in part on activating the second subset of memory cells; and reading one or more memory cells of the first portion of memory cells based at least in part on updating the first counter and the second counter.

18 . The method of claim 17 , further comprising:
comparing the second value of the updated second counter to a threshold stored at the controller, wherein reading one or more memory cells of the first portion of memory cells is based at least in part on comparing the second value of the updated second counter to the threshold.

19 . The method of claim 18 , wherein the comparing further comprises:
determining that the second value satisfies the threshold stored at the controller; stopping application of the second read voltage based at least in part on the determination that the second value satisfies the threshold; and identifying, from the second portion of memory cells, a total number of memory cells of the first portion having a first logic state based at least in part on the determination that the second value satisfies the threshold.

20 . The method of claim 19 , further comprising:
determining that the first value corresponds to the identified total number; and stopping application of the first read voltage based at least in part on the determination that the first value corresponds to the identified total number, wherein the one or more memory cells of the first portion of memory cells are read after application of the first read voltage has stopped.

21 . The method of claim 19 , further comprising:
determining that the first value does not correspond to the identified total number; and maintaining application of the first read voltage based at least in part on the determination that the first value does not correspond to the identified total number.

22 . The method of claim 18 , wherein the comparing further comprises:
determining that the second value does not satisfy the threshold stored at the controller; and maintaining application of the second read voltage based at least in part on the determination that the second value does not satisfy the threshold.

23 . The method of claim 17 , wherein the first read voltage and the second read voltage are a same single read voltage.

24 . The method of claim 17 , wherein the first read voltage is configured to have a time offset with respect to the second read voltage.

25 . The method of claim 17 , wherein the first read voltage is configured to have a different rate of voltage change with respect to the seco

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Amato Paolo
• Pio Federico
• Orlando Alessandro
• Sforzin Marco

Classifications

• G11C11/5678 Primary

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C13/003

  Cell access · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title