Protected runtime mode

Patent metadata

Field	Value
Publication number	US-2019196866-A1
Application number	US-201715852021-A
Country	US
Kind code	A1
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Jun 27, 2019
Grant date	—

Abstract

There is disclosed in one example a processor, including: a protected runtime mode (PRM) module to receive a PRM interrupt and to: suspend operation of a software task executing on the processor; save processor state information; place the microprocessor into PRM; access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task; restore the processor state; and resume operation of the software task.

First claim

What is claimed is:

1 . A processor, comprising:
a protected runtime mode (PRM) module to receive a PRM interrupt and to: suspend operation of a software task executing on the processor; save processor state information; place the microprocessor into PRM; access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task; restore the processor state; and resume operation of the software task.

2 . The processor of claim 1 , wherein accessing the PRM handler comprises accessing a PRM mailbox region comprising parameters for the PRM handler.

3 . The processor of claim 1 , wherein suspending operation of the software task comprises suspend only the core operating the software task.

4 . The processor of claim 1 , wherein suspending operation of the software task comprises suspending only the thread operating the software task.

5 . The processor of claim 1 , wherein accessing the PRM handler comprises blocking access to all system memory except for the PRM memory region.

6 . The processor of claim 1 , wherein the PRM memory region is defined by a PRM physical base register and a PRM mask register.

7 . The processor of claim 1 , wherein the PRM module is to update a PRM status register.

8 . The processor of claim 1 , wherein the PRM status register is a 256-bit status register comprising a single bit flag per thread.

9 . The processor of claim 1 , wherein the PRM module comprises microcode.

10 . The processor of claim 1 , wherein the PRM module comprises hardware instructions.

11 . The processor of claim 1 , wherein the PRM module comprises an intellectual property block.

12 . The processor of claim 1 , wherein the PRM module comprises an application-specific integrated circuit, a field-programmable gate array, or a co-processor.

13 . A computing system, comprising:
a basic input/output system (BIOS); a processor comprising a protected runtime mode (PRM) module to receive a PRM interrupt from the BIOS and to:
suspend operation of a software task executing on the processor;
save processor state information;
place the microprocessor into PRM;
access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task;
restore the processor state; and
resume operation of the software task.

14 . The computing system of claim 13 , wherein the BIOS is to issue the PRM interrupt responsive to a write to a port by an operating system of the computing system.

15 . The computing system of claim 14 , wherein the port is 0xB4.

16 . The computing system of claim 13 , wherein the PRM handler is visible to an operating system of the computing system.

17 . The computing system of claim 13 , wherein accessing the PRM handler comprises accessing a PRM mailbox region comprising parameters for the PRM handler.

18 . The computing system of claim 13 , wherein suspending operation of the software task comprises suspend only the core operating the software task.

19 . The computing system of claim 13 , wherein suspending operation of the software task comprises suspending only the thread operating the software task.

20 . The computing system of claim 13 , wherein accessing the PRM handler comprises blocking access to all system memory except for the PRM memory region.

21 . The computing system of claim 13 , wherein the PRM memory region is defined by a PRM physical base register and a PRM mask register.

22 . The computing system of claim 13 , wherein the PRM module is to update a PRM status register.

23 . The computing system of claim 13 , wherein the PRM status register is a 256-bit status register comprising a single bit flag per thread.

24 . The computing system of claim 13 , further comprising a virtual machine manager (VMM).

25 . The computing system of claim 13 , further comprising a containerization host.

26 . One or more tangible, non-transitory computer-readable mediums having stored thereon instructions to provide a protected runtime mode (PRM) module, the PRM module to:
suspend operation of a software task executing on the processor; save processor state information; place the microprocessor into PRM; access a PRM handler in a designated PRM memory region, wherein the PRM handler comprises a platform specific task; restore the processor state; and resume operation of the software task.

27 . The one or more tangible, non-transitory computer-readable mediums of claim 26 , wherein accessing the PRM handler comprises accessing a PRM mailbox region comprising parameters for the PRM handler.

Assignees

• Intel Corp

Inventors

• Kumar Mohan J
• Nachimuthu Murugasamy K
• Jayakumar Sarathy
• Ghetie Sergiu D
• Upasani Neeraj
• Story Ronald N

Classifications

• G06F9/485

  Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence) · CPC title

• G06F9/461 Primary

  Saving or restoring of program or task context · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F2213/0008

  High speed serial bus, e.g. Fiber channel · CPC title

• G06F2213/0024

  Peripheral component interconnect [PCI] · CPC title