Memory Arrays, and Methods of Forming Memory Arrays

Patent metadata

Field	Value
Publication number	US-2019172517-A1
Application number	US-201916267087-A
Country	US
Kind code	A1
Filing date	Feb 4, 2019
Priority date	Nov 6, 2017
Publication date	Jun 6, 2019
Grant date	—

Abstract

Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.

First claim

1 - 26 . (canceled)

27 : An assembly comprising:
an active material structure including a bit contact region and a cell contact region; a first redistribution pad coupled with the bit contact region; a second redistribution pad coupled with the cell contact region; a bitline over the active material structure and electrically connected with the first redistribution pad; a programmable device over the active material structure and electrically connected with the second redistribution pad; and wherein the first redistribution pad is horizontally expanded relative to the bit contact region to allow the bitline to be horizontally offset relative to the bit contact region.

28 : The assembly of claim 27 , wherein the programmable device comprises a capacitor.

29 : The assembly of claim 27 , wherein the active material structure comprises monocrystalline silicon, and wherein each of the first and second redistribution pads comprises polycrystalline silicon.

30 : The assembly of claim 27 , further comprising a conductive plug between the second redistribution pad and the programmable device, wherein the conductive plug is approximately vertically aligned with the cell contact region.

31 : The assembly of claim 30 , wherein each of the bitline and the conductive plug comprises a metal.

32 : The assembly of claim 30 , wherein an upper surface of the bitline is recessed downwardly relative to an upper surface of the conductive plug.

33 : The assembly of claim 27 , wherein an upper surface of the bit contact region is vertically offset relative to an upper surface of the cell contact region.

34 : The assembly of claim 33 , wherein the upper surface of the bit contact region is recessed downwardly relative to the upper surface of the cell contact region.

35 : A memory array, comprising:
wordlines extending along a first direction; bitlines extending along a second direction that crosses the first direction; active material structures at regions where the wordlines and bitlines cross one another, each of the active material structures having a bit contact region and a cell contact region; first redistribution pads coupled with the bit contact regions; second redistribution pads coupled with the cell contact regions; each of the bit contact regions being coupled with an associated one of the bitlines at least partially through one of the first redistribution pads; the first redistribution pads being horizontally expanded relative to the bit contact regions to allow the associated bitlines to be horizontally offset relative to the bit contact regions; programmable devices coupled with the cell contact regions at least partially through the second redistribution pads; the active material structures comprising a first material; and the first and second redistribution pads comprising a second material which is different from the first material.

36 : The memory array of claim 35 wherein the programmable devices are capacitors.

37 : The memory array of claim 35 wherein the bit contact regions are vertically offset relative to the cell contact regions.

38 : The memory array of claim 35 wherein the bit contact regions are not vertically offset relative to the cell contact regions.

39 : The memory array of claim 35 wherein the first material comprises monocrystalline silicon, and wherein the second material comprise polycrystalline silicon.

40 : The memory array of claim 35 wherein the first material of the active material structures is entirely covered by the second material of the first and second redistribution pads.

41 : The memory array of claim 35 wherein the first material of the active material structures is not entirely covered by the second material of the first and second redistribution pads.

42 : A method of forming a DRAM array, comprising:
forming active material structures which each have a bit contact region and a cell contact region; the active material structures being arranged in an array having rows and columns; the rows extending along a first direction, and the columns extending along a second direction which intersects the first direction; forming first redistribution material over the active material structures; forming first protective material over the first redistribution material; patterning the first redistribution material and the first protective material into stripes which extend along the second direction, the stripes being over the cell contact regions and not over the bit contact regions; forming second protective material along sides of the stripes; the first protective material, second protective and first redistribution material of the stripes together forming first linear structures that extend along the second direction and over the cell contact regions; first trenches being between the first linear structures, and the bit contact regions being exposed within the first trenches; forming second redistribution material within the first trenches between the first linear structures; the second redistribution material being configured as second linear structures extending along the second direction; forming second trenches through the first and second linear structures and extending along the first direction, the second trenches cutting the second redistribution material of the second linear structures into first redistribution pads, and cutting the first redistribution material of the first linear structures into second redistribution pads; forming wordlines within the second trenches; forming third protective material within the second trenches and over the wordlines; forming bitlines extending along the second direction and coupled with the first redistribution pads; and forming programmable devices coupled with the second redistribution pads.

43 : The method of claim 42 wherein upper surfaces of at least some the cell contact regions are exposed through the second redistribution pads and are coupled with the programmable devices.

44 : The method of claim 42 wherein upper surfaces of at least some the bit contact regions are exposed through the first redistribution pads and are directly against the bitlines.

45 : The method of claim 42 comprising recessing the bit contact regions relative to the cell contact regions.

46 : The method of claim 42 comprising recessing the bit contact regions within the first trenches prior to forming the second redistribution material.

47 : The method of claim 42 wherein the active material structures comprise pillars of monocrystalline silicon.

48 : The method of claim 42 wherein the first and second redistribution materials are conductively-doped silicon.

49 : The method of claim 42 wherein the first, second and third protective materials comprise silicon nitride.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Wang Kuo-Chen
• Roberts Martin C
• Tran Diem Thy N
• Gomi Hideki
• Fishburn Fredrick D
• Pulugurtha Srinivas
• Koopmans Michel
• Hasunuma Eiji

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/4023 Primary

  using field effect transistors · CPC title

• H01L27/10847

  Electricity · mapped topic

• H01L27/10805

  Electricity · mapped topic

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title