Successive approximation register analog-digital converter and sar adc system

Patent metadata

Field	Value
Publication number	US-2019166325-A1
Application number	US-201816204963-A
Country	US
Kind code	A1
Filing date	Nov 29, 2018
Priority date	Nov 29, 2017
Publication date	May 30, 2019
Grant date	—

Abstract

A successive approximation register (SAR) analog-digital converter (ADC) may include a comparison circuit coupled to an array of pixels arranged in rows and columns to receive a first pixel signal and a second pixel signal from a first column and a second column, respectively, and structured to compare each of the first and second pixel signals with a reference voltage and output comparison signals; an analog-digital conversion mode decision circuit located to receive the comparison signals from the comparison circuit and structure to provide a mode decision value which decides an analog-digital conversion mode out of different analog-digital conversion modes based on the comparison signals from the comparison circuit; and a shared circuit shared by the first and second columns, and structured to generate the reference voltage based on the comparison signals from the comparison circuit and the mode decision value from the analog-digital conversion mode decision circuit, the shared circuit outputting the reference voltage to the comparison circuit.

First claim

What is claimed is:

1 . A successive approximation register (SAR) analog-digital converter (ADC) comprising:
a comparison circuit coupled to an array of pixels arranged in rows and columns to receive a first pixel signal and a second pixel signal from a first column and a second column, respectively, and structured to compare each of the first and second pixel signals with a reference voltage and output comparison signals; an analog-digital conversion mode decision circuit located to receive the comparison signals from the comparison circuit and structure to provide a mode decision value which decides an analog-digital conversion mode out of different analog-digital conversion modes based on the comparison signals from the comparison circuit; and a shared circuit shared by the first and second columns, and structured to generate the reference voltage based on the comparison signals from the comparison circuit and the mode decision value from the analog-digital conversion mode decision circuit, the shared circuit outputting the reference voltage to the comparison circuit.

2 . The SAR ADC of claim 1 , wherein the analog-digital conversion mode is either an LSB (Least Significant Bit) analog-digital conversion in which only some of bits of an analog-digital conversion value of a target pixel signal are converted or a full analog-digital conversion in which all bits of the analog-digital conversion value of the target pixel signal are analog-digital converted.

3 . The SAR ADC of claim 1 , wherein the comparison circuit comprises:
a first comparator located to receive the first pixel signal from the first column and structured to compare the first pixel signal with the reference voltage from the shared circuit, and output a first comparison signal; and a second comparator located to receive the second pixel signal and structured to compare the second pixel signals with the reference voltage from the shared circuit, and output a second comparison signal.

4 . The SAR ADC of claim 3 ,
wherein the analog-digital conversion mode decision circuit comprises: a first analog-digital conversion mode decider located to receive the first comparison signal from the comparison circuit and structured to decide the analog-digital conversion mode based on the received first comparison signal and a value obtained by comparing most significant bits (MSBs) of an analog-digital conversion value of a previous column pixel signal with a current column pixel signal; and a second analog-digital conversion mode decider located to receive the second comparison signal from the comparison circuit and structured to decide the analog-digital conversion mode based on the received second comparison signal and the value obtained by comparing the MSBs of the analog-digital conversion value of a previous column pixel signal with a current column pixel signal.

5 . The SAR ADC of claim 1 , wherein the analog-digital conversion mode decision circuit provides the mode decision value based on a comparison between the first pixel signal and a previous column pixel signal prior to the first pixel signal or between the second pixel signal and another previous column pixel signal prior to the second pixel signal.

6 . The SAR ADC of claim 1 , wherein the shared circuit comprises:
a shared SAR operation logic circuit located to receive the mode decision value from the analog-digital conversion mode, and configured to output a control signal to conduct the LSB analog-digital conversion or full analog-digital conversion; a shared MSB storage and update circuit receiving the control signal from the shared SAR operation logic circuit and storing MSB information of an analog-digital conversion value of the first pixel signal; a shared ranging circuit receiving the control signal from the shared SAR operation logic circuit and outputting a ranging control value for generating the reference voltage; the shared storage circuit receiving the ranging control value from the shared ranging circuit and outputting an analog-digital conversion value including the MSB information and a LSB information; and a shared capacitor digital-analog converter (C-DAC) receiving the analog-digital conversion value from the shared storage circuit and generating the reference voltage.

7 . The SAR ADC of claim 6 , wherein the shared SAR operation logic circuit conduct the LSB analog-digital conversion or full analog-digital conversion according to the output values of the comparison circuit and the analog-digital conversion mode decision circuit,
wherein the shared MSB storage and update circuit copies the MSB information of the analog-digital conversion value to the shared storage circuit and updates the MSB information according to a comparison result value of the comparison circuit, wherein the shared ranging circuit outputs the value obtained by comparing the MSB information of an analog-digital conversion value of a previous column pixel signal with a current column pixel signal, wherein the shared storage circuit stores the comparison result value of the comparison circuit, and wherein the shared C-DAC outputs the reference voltage to a first comparator and a second comparator of the comparison circuit.

8 . The SAR ADC of claim 6 , wherein the shared storage circuit stores at least one of the MSB information, the LSB information, or the ranging control value.

9 . The SAR ADC of claim 6 , wherein the MSBs information corresponds to a common voltage value for conducting an analog-digital conversion of the first pixel signal.

10 . The SAR ADC of claim 6 , wherein the MSB information corresponds to a pixel signal code value of a previous row that is prior to a current row.

11 . The SAR ADC of claim 1 , wherein the first column and the second column are selected during a same period and a validity of MSBs of a previous signal is checked during the same period.

12 . The SAR ADC of claim 1 ,
wherein the comparison circuit is coupled to further receive a third pixel signal from a third column and structured to compare the third pixel signal with the reference voltage, and the shared circuit is shared by the third circuit.

13 . A successive approximation register (SAR) analog-digital converter (ADC) system comprising:
a comparison circuit coupled to an array of pixels arranged in rows and columns to receive a first pixel signal and a second pixel signal from a first column and a second column, respectively, and structured to compare each of the first and second pixel signals with a reference voltage and output comparison signals; an analog-digital conversion mode decision circuit located to receive the comparison signals from the comparison circuit and structure to provide a mode decision value which decides an analog-digital conversion mode out of different analog-digital conversion modes based on the comparison signals from the comparison circuit; and a shared circuit shared by the first and second columns, and structured to generate the reference voltage based on the comparison signals from the comparison circuit and the mode decision value from the analog-digital conversion mode decision circuit, the shared circuit outputting the reference voltage to the comparison circuit; and a shared column selection circuit providing a column selection signal to the comparison circuit to enable the first column or the second column, the shared column selection circuit configured to control the analog-digital conversion mode decision circuit and the shared circuit.

14 . The SAR ADC system of claim 13 , wherein the comparison circuit comprises:
a first comparator located to receive

Assignees

• Sk Hynix Inc

Inventors

• Kim Hyeon-June

Classifications

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H03M1/406 Primary

  using current mode circuits, i.e. circuits in which the information is represented by current values rather than by voltage values · CPC title