Switching unit for voltage inverter or rectifier

Patent metadata

Field	Value
Publication number	US-2019149064-A1
Application number	US-201816184953-A
Country	US
Kind code	A1
Filing date	Nov 8, 2018
Priority date	Nov 10, 2017
Publication date	May 16, 2019
Grant date	—

Abstract

A neutral point clamped multiple-level switching unit is disclosed, including four series-connected switches, where the electric path in the four switches approximately follows a T shape, two of the switches located in the middle of the series association being arranged in the foot of the T.

First claim

What is claimed is:

1 . A neutral point clamped multiple-level switching unit comprising four series-connected switches (K 1 , K 2 , K 3 , K 4 ), wherein the electric path in the four switches approximately follows a T shape, two (K 2 , K 3 ) of the switches located in the middle of the series association being arranged in the foot of the T, each of said two switches (K 2 , K 3 ) is series-connected with a diode (Dh, Dl) between a first output terminal ( 15 ) and a second output terminal ( 17 ) of the unit.

2 . The unit of claim 1 , wherein said two switches (K 2 , K 3 ) are arranged to, when they conduct a same current, mutually compensate (MI) their respective parasitic inductances.

3 . The unit of claim 1 , wherein a node between said two switches (K 2 , K 3 ) defines a first output terminal ( 15 ) of the unit.

4 . The unit of claim 3 , wherein:
the series association of the four switches (K 1 , K 2 , K 3 , K 4 ) is connected between two input terminals ( 11 , 13 ) of the unit; a node ( 16 ) between a first switch (K 1 ) and a second switch (K 2 ) is coupled, by a first diode (Dh), to a second output terminal ( 17 ) of the unit; a node ( 18 ) between a third switch (K 3 ) and a fourth switch (K 4 ) is coupled, by a second diode (Dl), to the second output terminal ( 17 ) of the unit, said two switches being the second and third switches.

5 . The unit of claim 4 , wherein the first and second diodes (Dh Dl) are connected to separate nodes ( 171 , 172 ), interconnected to the second output terminal ( 17 ).

6 . The unit of claim 1 , formed on at least one printed circuit wafer ( 60 ; 61 , 62 ) defining conductive areas for receiving components and contact transfer wires.

7 . The unit of claim 6 , wherein first surfaces of the switches (K 1 , K 2 , K 3 , K 4 ) and diodes (Dh, Dl) are coplanar.

8 . The unit of claim 7 , wherein four conductive areas ( 611 , 616 , 615 , 618 ) each support one of the switches (K 1 , K 2 , K 3 , K 4 ).

9 . The unit of claim 8 , comprising two coplanar wafers ( 61 , 62 ) respectively receiving at least the first and second switches (K 1 , K 2 ) and the third and fourth switches (K 3 , K 4 ), each wafer comprising a conductive area ( 612 , 617 ) defining one of the nodes ( 171 , 172 ) of connection of one of the diodes (Dh, Dl).

10 . The unit of claim 1 , wherein each switch (K 1 , K 2 , K 3 , K 4 ) is associated with a diode (D 1 , D 2 , D 3 , D 4 ) assembled in parallel.

11 . The unit of claim 1 , wherein the switches (K 1 , K 2 , K 3 , K 4 ) are semiconductor components, preferably MOS or IGBT transistors.

12 . The unit of claim 10 , wherein each diode (D 1 , D 2 , D 3 , D 4 ) assembled in parallel with a switch (K 1 , K 2 , K 3 , K 4 ) is the intrinsic diode of the transistor.

13 . The unit of claim 1 , wherein each switch (K 1 , K 2 , K 3 , K 4 ) is formed of a plurality of semiconductor chips electrically in parallel.

14 . A power converter comprising:
at least one switching unit ( 1 ) of claim 1 ; and at least one capacitive dividing bridge (C 1 , C 2 ).

15 . The converter of claim 14 , wherein the capacitive dividing bridge comprises two capacitive elements (C 1 , C 2 ) series-connected between input terminals ( 11 , 13 ), a node ( 12 ) between the two capacitive elements being coupled to the second output terminal ( 15 ).

Assignees

• Commissariat Energie Atomique

Inventors

• Lefevre Guillaume

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/00

  Package configurations · CPC title