Method of forming semiconductor device using titanium-containing layer and device formed

US2019148152A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019148152-A1
Application numberUS-201816231836-A
CountryUS
Kind codeA1
Filing dateDec 24, 2018
Priority dateDec 14, 2016
Publication dateMay 16, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of forming a semiconductor device, the method comprising: depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D; and annealing the semiconductor device to form a silicide layer in the S/D and in the protrusions. 2 . The method of claim 1 , wherein the depositing comprises performing a sputtering process using a bias power ranging from about 50 Watts (W) to 1000 W. 3 . The method of claim 1 , wherein the depositing comprises using a plasma power ranging from about 50 W to about 10,000 W. 4 . The method of claim 1 , wherein the annealing is performed at a temperature ranging from about 500° C. to about 600° C. 5 . The method of claim 1 , wherein the annealing is performed for a duration ranging from about 20 seconds to about 60 seconds. 6 . A device comprising: a source/drain (S/D) in a substrate and adjacent to a gate structure, wherein the S/D comprises a protrusion extending from a top surface of the S/D, and the protrusion has a tapered profile; a silicide layer in the protrusion, wherein the silicide layer comprises titanium; and a contact plug electrically connected to the protrusion through the silicide layer. 7 . The device of claim 6 , wherein a height of the protrusion above the top surface of the S/D ranges from about 3 nanometers (nm) to about 7 nm. 8 . The device of claim 6 , wherein a width of the protrusion closest to the top surface of the S/D ranges from about 4 nm to about 6 nm. 9 . The device of claim 6 , wherein a width of the protrusion farthest to the top surface of the S/D ranges from about 0.5 nm to about 1.5 nm. 10 . The device of claim 6 , wherein the silicide layer extends along the top surface of the S/D. 11 . A device comprising: a gate structure over a substrate; a source/drain (S/D) in the substrate adjacent to the gate structure, wherein the S/D comprises at least one protrusion extending from a top surface of the S/D; a silicide layer extending along the at least one protrusion and along the top surface of the S/D; and a contact plug electrically connected to the at least one protrusion and the S/D through the silicide layer. 12 . The device of claim 11 , wherein a width of the at least one protrusion is constant as a distance from the S/D increases. 13 . The device of claim 11 , wherein the at least one protrusion comprises a plurality of protrusions, and the silicide layer extends along each protrusion of the plurality of protrusions. 14 . The device of claim 11 , further comprising an inter-layer dielectric (ILD) over the S/D. 15 . The device of claim 14 , wherein the top surface of the S/D contacting the silicide layer is recessed with respect to a top surface of the S/D under the ILD. 16 . The device of claim 14 , wherein the at least one protrusion extends along the ILD. 17 . The device of claim 11 , wherein a height of the protrusion above the top surface of the S/D ranges from about 3 nanometers (nm) to about 7 nm. 18 . The device of claim 11 , wherein the S/D comprises germanium. 19 . The device of claim 11 , wherein the at least one protrusion has a tapered profile. 20 . The device of claim 11 , wherein a concentration of germanium in the S/D varies along a direction parallel to a top surface of the substrate.

Assignees

Inventors

Classifications

  • Physical vapour deposition [PVD] · CPC title

  • using a gas or vapour · CPC title

  • the openings being via holes penetrating underlying conductors · CPC title

  • by forming self-aligned vias or self-aligned contact plugs · CPC title

  • by introducing additional elements therein · CPC title

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What does patent US2019148152A1 cover?
A method of forming a semiconductor device includes depositing a titanium-containing material over a source/drain (S/D), wherein an energy of depositing the titanium-containing material is sufficient to cause re-deposition of a material of the S/D along sidewalls of a dielectric layer adjacent the S/D to form protrusions extending from a top surface of the S/D. The method further includes annea…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D64/0112. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu May 16 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).