Temporarily storing memory contents

Patent metadata

Field	Value
Publication number	US-2019121736-A1
Application number	US-201816167985-A
Country	US
Kind code	A1
Filing date	Oct 23, 2018
Priority date	Oct 24, 2017
Publication date	Apr 25, 2019
Grant date	—

Abstract

A memory arrangement having a memory, a first buffer memory, a first buffer memory controller which, during the storage of memory contents from the memory in the first buffer memory, is configured to invalidate the memory contents in the memory by means of a modification, a second buffer memory and a second buffer memory controller which is configured to read memory contents from the memory, to check whether the memory contents read from the memory are valid and, if the memory contents read from the memory are invalid, to apply a reversal of the modification to the read memory contents.

First claim

1 . A memory arrangement, comprising:
a memory; a first buffer memory; a first buffer memory controller which is configured, during the storage of memory contents from the memory in the first buffer memory, to invalidate the memory contents in the memory by means of a modification; a second buffer memory; and a second buffer memory controller which is configured to read the memory contents from the memory, to check whether the memory contents read from the memory are valid and, if the memory contents read from the memory are invalid, to apply a reversal of the modification to the read memory contents.

2 . The memory arrangement as claimed in claim 1 , wherein the second buffer memory controller is configured to store the read memory contents modified by means of the reversal of the modification in the second buffer memory.

3 . The memory arrangement as claimed in claim 1 , wherein the memory contents include instructions and data to be processed by means of the instructions, and the first buffer memory is a buffer memory configured to provide data to be processed to a processor and the second buffer memory is a buffer memory configured to provide instructions to the processor.

4 . The memory arrangement as claimed in claim 1 , wherein error code information is stored for the memory contents in the memory, and the first buffer memory controller is configured to invalidate the memory contents in the memory by means of a modification of the stored error code information.

5 . The memory arrangement as claimed in claim 4 , wherein the second buffer memory controller is configured to check, on the basis of the stored error code information, whether the memory contents read from the memory are valid.

6 . The memory arrangement as claimed in claim 5 , wherein the second buffer memory controller is configured to check whether the memory contents read from the memory are valid by checking whether the memory contents are error free according to the stored error code information.

7 . The memory arrangement as claimed in claim 6 , wherein the application of the reversal of the modification comprises checking whether the memory contents are error-free according to error code information resulting from the stored error code information through application of the reversal of the modification.

8 . The memory arrangement as claimed in claim 1 , wherein the memory contents are a data block and the first buffer memory and the second buffer memory are configured to temporarily store memory contents in data blocks.

9 . The memory arrangement as claimed in claim 1 , wherein the modification of the memory contents comprises modifying one or more bits of the memory contents or one or more bits of error code information of the memory contents.

10 . The memory arrangement as claimed in claim 1 , wherein the first buffer memory controller has read and write access to the memory, and the second buffer memory controller has read-only access to the memory.

11 . The memory arrangement as claimed in claim 1 , wherein the modification is irreversible for the first buffer memory controller and is reversible for the second buffer memory controller.

12 . The memory arrangement as claimed in claim 1 , wherein a prediction bit which indicates whether the memory contents have been modified is stored for the memory contents in the memory, and the first buffer memory controller is configured to set the prediction bit during the reading or modification of the memory contents.

13 . The memory arrangement as claimed in claim 12 , wherein the second buffer memory controller is configured to check, on the basis of the stored prediction bit, whether the memory contents read from the memory are valid.

14 . A method for temporarily storing memory contents, comprising:
during the storage of memory contents from a memory in a first buffer memory, modifying, by a first buffer memory controller, the memory contents in the memory so that they are invalidated; reading, by a second buffer memory controller, the memory contents from the memory for storing the memory contents in a second buffer memory; checking, by the second buffer memory controller, whether the memory contents read from the memory are valid; and if the memory contents read from the memory are invalid, applying, by the second buffer memory controller, a reversal of the modification to the real memory contents.

15 . The method as claimed in claim 14 , further comprising:
storing, by the second buffer memory controller, the read memory contents modified by means of the reversal of the modification in the second buffer memory.

16 . The method as claimed in claim 14 ,
wherein error code information is stored for the memory contents in the memory, and further comprising invalidating, by the first buffer memory controller, the memory contents in the memory by means of a modification of the stored error code information.

17 . The method of claim 16 , further comprising:
checking, by the second buffer memory controller, whether the memory contents read from the memory are valid, on the basis of the stored error code information.

18 . The method of claim 17 , wherein the application of the reversal of the modification comprises:
checking whether the memory contents are error-free according to error code information resulting from the stored error code information through application of the reversal of the modification.

19 . The method of claim 14 ,
wherein the memory contents are a data block, further comprising temporarily storing, by the first buffer memory and the second buffer memory, memory contents in data blocks.

20 . The method of claim 14 , wherein the modification is irreversible for the first buffer memory controller and is reversible for the second buffer memory controller.

Assignees

• Infineon Technologies Ag

Inventors

• Sonnekalb Steffen

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0808 Primary

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title