Semiconductor device

Patent metadata

Field	Value
Publication number	US-2019109210-A1
Application number	US-201816195683-A
Country	US
Kind code	A1
Filing date	Nov 19, 2018
Priority date	Aug 29, 2015
Publication date	Apr 11, 2019
Grant date	—

Abstract

A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a III-V compound layer; a source contact and a drain contact over the III-V compound layer; a gate contact over the III-V compound layer and between the source contact and the drain contact; a gate field plate over the III-V compound layer; a first etch stop layer over the source contact; and a second etch stop layer over the drain contact and separated from the first etch stop layer.

2 . The semiconductor device of claim 1 , wherein a top surface of the gate field plate is lower than a top surface of the gate contact.

3 . The semiconductor device of claim 1 , further comprising:
a first anti-reflective coating (ARC) layer between the first etch stop layer and the source contact; and a second ARC layer between the second etch stop layer and the drain contact, wherein the first ARC layer is separated from the second ARC layer.

4 . The semiconductor device of claim 3 , wherein the first ARC layer and the gate field plate comprises the same material.

5 . The semiconductor device of claim 3 , further comprising:
a third ARC layer over the gate contact.

6 . The semiconductor device of claim 1 , further comprising:
a protection layer surrounding the source contact, the drain contact, and a bottom portion of the gate contact; and a dielectric layer surrounding a top portion of the gate contact.

7 . A semiconductor device comprising:
a first semiconductor layer; a second semiconductor layer over the first semiconductor layer; a source/drain contact over the second semiconductor layer; a gate contact over the second semiconductor layer; a gate field plate over the second semiconductor layer; a first anti-reflective coating (ARC) layer over the source/drain contact; a second ARC layer over the gate contact and separated from the first ARC layer; and an etch stop layer over the first ARC layer.

8 . The semiconductor device of claim 7 , wherein the gate field plate is free from coverage by the etch stop layer.

9 . The semiconductor device of claim 7 , wherein the second ARC layer is free from coverage by the etch stop layer.

10 . The semiconductor device of claim 7 , wherein a sidewall of the etch stop layer is substantially aligned with a sidewall of the first ARC layer.

11 . The semiconductor device of claim 7 , wherein a sidewall of the first ARC layer is substantially aligned with a sidewall of the source/drain contact.

12 . The semiconductor device of claim 7 , wherein a sidewall of the second ARC layer is substantially aligned with a sidewall of the gate contact.

13 . The semiconductor device of claim 7 , further comprising a conductive contact separated from the source/drain contact by the first ARC layer.

14 . The semiconductor device of claim 7 , further comprising:
a dielectric layer over the second semiconductor layer, wherein a top surface of the dielectric layer is lower than a top surface of the source/drain contact, and the gate field plate is in contact with the top surface of the dielectric layer.

15 . The semiconductor device of claim 7 , further comprising:
a first oxide layer over the etch stop layer, wherein the etch stop layer comprises an oxide; and a second oxide layer over the first oxide layer.

16 . A semiconductor device comprising:
a first III-V compound layer; a second III-V compound layer over the first III-V compound layer; a source/drain contact over the second III-V compound layer; a gate contact over the second III-V compound layer; a gate field plate over the second III-V compound layer; a first anti-reflective coating (ARC) layer over the source/drain contact; and an etch stop layer over the first ARC layer and separated from the gate field plate.

17 . The semiconductor device of claim 16 , wherein the gate contact is free from coverage by the etch stop layer.

18 . The semiconductor device of claim 16 , further comprising:
a second ARC layer over the gate contact.

19 . The semiconductor device of claim 18 , further comprising:
a conductive contact in contact with the second ARC layer, wherein the conductive contact is separated from the gate contact by the second ARC layer.

20 . The semiconductor device of claim 18 , further comprising:
a dielectric layer surrounding the gate contact and in contact with the second ARC layer; and a protection oxide layer between the dielectric layer and the source/drain contact, wherein a top surface of the first ARC layer is separated from the dielectric layer by the protection oxide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• You Jheng-Sheng
• Lin Hsin-Chih
• Huang Kun-Ming
• Chen Lieh-Chuan
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H01L29/402

  Electricity · mapped topic

• H01L29/7786

  Electricity · mapped topic

• H01L29/41758

  Electricity · mapped topic

• H01L29/452

  Electricity · mapped topic

• H01L29/1066

  Electricity · mapped topic