Binary, ternary and bit serial compute-in-memory circuits

Patent metadata

Field	Value
Publication number	US-2019102359-A1
Application number	US-201816147036-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 4, 2019
Grant date	—

Abstract

A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a memory array of memory cells to store a binary weight matrix; a memory access circuit of bitlines having equal capacitance and wordlines driven with pulses of fixed duration to activate one or more memory cells in the memory array based on an input vector, wherein the memory access circuit to enable an activated bitcell in the memory array to cause a voltage drop in a bitline to which the activated bitcell is coupled, wherein the voltage drop is equivalent to voltage drops caused by other activated memory cells in the memory array; and a capacitor circuit coupled to the bitlines to accumulate bitline voltages after voltage drops into a voltage output, the voltage output to represent a dot product of the input vector and the binary weight matrix stored in the memory array.

2 . The integrated circuit of claim 1 , the memory access circuit including a wordline driver to modulate the pulses of fixed duration based on the input vector, wherein the pulses to activate the one or more memory cells in the memory array based on binary weights of the binary weight matrix, the binary weights stored in the memory cells.

3 . The integrated circuit of claim 2 , wherein the memory array is to store multibit binary weights as a thermometer weight scalar in a same memory row of the memory array, wherein the thermometer weight scalar is to enable the voltage output to represent the dot product of the input vector and the binary weight matrix with an increase in precision.

4 . The integrated circuit of claim 2 , wherein the memory access circuit is further to:
receive an input vector representing a multibit value stored as a thermometer input scalar; replicate binary weights of the binary weight matrix across multiple rows of the memory array of memory cells, the multiple rows corresponding to a dimension of the thermometer input scalar; and the wordline driver to modulate the pulses of fixed duration across all of the multiple rows to enable the voltage output to represent the dot product of the input vector and the binary weight matrix with an increase in precision.

5 . The integrated circuit of claim 2 , wherein:
the input vector represents a multibit integer input value; and the capacitor circuit includes a bit serial accumulation capacitor to perform an analog bit serial accumulation operation for each bit of the multibit integer input value.

6 . The integrated circuit of claim 5 , wherein to perform the analog bit serial accumulation operation the capacitor circuit is to accumulate and shift values of output vectors obtained from dot products of each bit of a multibit integer input vector and the binary weight matrix, wherein accumulated and shifted values represent the dot product of the input vector and the binary weight matrix.

7 . The integrated circuit of claim 1 , the capacitor circuit including:
a column switch capacitor coupled to a bitline to accumulate a bitline voltage after voltage drops caused by activated memory cells coupled to the bitline, an accumulated bitline voltage not exceeding an allowable voltage swing; and wherein the accumulated bitline voltage represents a positive integer value of an output vector equal to the dot product of the input vector and the binary weight matrix.

8 . The integrated circuit of claim 1 , wherein:
binary weights of the binary weight matrix include multibit binary weights stored as binary integers in a row of consecutive memory cells spanning multiple columns of the memory array; and the capacitor circuit includes a weighted column switch capacitor for each column of memory cells, the weighted column switch capacitor capable of charge sharing with neighboring capacitors spanning the multiple columns of the memory array, the capacitor circuit to: disconnect a binary weighted fraction of each weighted column switch capacitor during charge sharing with neighboring capacitors, wherein the binary weighted fraction of each weighted column switch capacitor represents a ratio of weighted column switch capacitors across neighboring capacitors, the ratio based on a power of two.

9 . The integrated circuit of claim 1 , wherein:
bitlines of the memory access circuit include differential bitlines to double an allowable voltage swing caused by activated memory cells; binary weights of the binary weight matrix include signed binary weights, wherein the activated bitcell in which a signed binary weight is stored is enabled to cause voltage drops to the differential bitlines; and the capacitor circuit coupled to the differential bitlines includes a differential column switch capacitor for each column of the memory array, the differential column switch capacitor to:
accumulate differential bitline voltages after voltage drops, an accumulated differential bitline voltage not exceeding a doubled allowable voltage swing;
determine a differential voltage output between the accumulated differential bitline voltage; and
wherein the differential voltage output for each column of the memory array represents a signed integer value of an output vector equal to the dot product of the input vector and the binary weight matrix.

10 . The integrated circuit of claim 9 , wherein the input vector represents a ternary input value and:
a first pulse of fixed duration based on the input vector represents a ternary value of one, the first pulse to enable activated memory cells to cause voltage drops in a first one of the differential bitlines; a second pulse of fixed duration based on the input vector represents a ternary value of negative one, the second pulse to enable activated memory cells to cause voltage drops to a second one of the differential bitlines; and no pulse based on the input vector representing a zero ternary value to enable no memory cells to cause voltage drops to any of the differential bitlines.

11 . The integrated circuit of claim 9 , wherein:
binary weights of the binary weight matrix include multibit binary weights stored as signed binary integers, wherein the activated memory cells in which the signed binary integers are stored are enabled to cause voltage drops in the differential bitlines; and the capacitor circuit includes a negation circuit coupled to a column of the memory array corresponding to a bitcell in which a most significant bit of a multibit binary weight is stored, the negation circuit to invert an accumulated differential bitline voltage caused by the activated memory cells.

12 . The integrated circuit of claim 9 , wherein:
binary weights of the binary weight matrix include multibit binary weights stored as signed binary integers, wherein the activated memory cells in which the signed binary integers are stored are enabled to cause voltage drops in the differential bitlines; and the capacitor circuit includes a weighted differential column switch capacitor coupled to a column of the memory array, the weighted differential column switch capacitor capable of charge sharing with neighboring capacitors spanning multiple columns of the memory array, the capacitor circuit further to: disconnect a binary weighted fraction of each weighted differential column switch capacitor during charge sharing of neighboring capacitors, wherein the binary weighted fraction of each weighted differential column switch capacitor represents a ratio of weighted differential column switch capacitors across neighboring capacitors, the ratio based on a power of two; and wherein the capacitor circuit further includes a negation circuit to swap the differential voltage output for each column of the memory array.

13 . The integrated

Assignees

• Intel Corp

Inventors

• Knag Phil
• Chen Gregory K
• Kumar Raghavan
• Sumbul Huseyin Ekin
• Sharma Abhishek
• Manipatruni Sasikanth
• Mathuriya Amrita
• Krishnamurthy Ram A
• Young Ian A

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title