Gate all around device and fabrication thereof

Patent metadata

Field	Value
Publication number	US-2019097010-A1
Application number	US-201715719301-A
Country	US
Kind code	A1
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Mar 28, 2019
Grant date	—

Abstract

A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.

First claim

1 . A device, comprising:
a nanowire having a sidewall; a gate dielectric layer surrounding the nanowire; and a gate electrode surrounding the gate dielectric layer and separated from the nanowire, the gate electrode comprising a sloped sidewall inclined with respect to the sidewall of the nanowire.

2 . The device of claim 1 , further comprising:
a conductive layer under and in contact with the gate electrode, the sloped sidewall of the gate electrode is inclined with respect to a top surface of the conductive layer.

3 . The device of claim 2 , further comprising:
a gate contact in contact with the sloped sidewall of the gate electrode and the top surface of the conductive layer.

4 . The device of claim 1 , further comprising:
a gate contact in contact with the sloped sidewall of the gate electrode.

5 . The device of claim 1 , further comprising:
a conductive layer laterally extending across the sloped sidewall of the gate electrode and in contact with a bottom edge of the sloped sidewall.

6 . The device of claim 5 , further comprising:
a gate contact in contact with the conductive layer.

7 . The device of claim 1 , further comprising:
a gate contact electrically coupled to the gate electrode; and a dielectric structure having a first sidewall in contact with the sloped sidewall of the gate electrode and a second sidewall in contact with the gate contact, wherein the first sidewall is inclined with respect to the second sidewall.

8 . The device of claim 1 , wherein the gate electrode further comprises an inner sidewall between the sloped sidewall and the nanowire, wherein the sloped sidewall is inclined with respect to the inner sidewall.

9 . The device of claim 1 , wherein the gate electrode further comprises top and bottom surfaces connected by the sloped sidewall, and the top surface has a width less than a width of the bottom surface.

10 . The device of claim 1 , wherein the gate dielectric layer has an outer sidewall in contact with the gate electrode, wherein the sloped sidewall of the gate electrode is inclined with respect to the outer sidewall of the gate dielectric layer.

11 . The device of claim 1 , further comprising:
a conductive layer under the nanowire and electrically isolated from the gate electrode; a source/drain contact in contact with the conductive layer; and a dielectric structure between the sloped sidewall of the gate electrode and the source/drain contact.

12 . The device of claim 11 , wherein the dielectric structure has a first sidewall in contact with the sloped sidewall of the gate electrode and a second sidewall in contact with the source/drain contact, wherein the first sidewall is inclined with respect to the second sidewall.

13 . A device, comprising:
a conical frustum-shaped gate electrode; a nanowire extending through the conical frustum-shaped gate electrode, the nanowire comprising a sidewall non-parallel to an outer sidewall of the conical frustum-shaped gate electrode; and a gate dielectric layer between the conical frustum-shaped gate electrode and the nanowire.

14 . The device of claim 13 , wherein the gate dielectric layer comprises a sidewall non-parallel to the outer sidewall of the conical frustum-shaped gate electrode.

15 . The device of claim 13 , wherein the conical frustum-shaped gate electrode has an inner sidewall non-parallel to the outer sidewall of the conical frustum-shaped gate electrode.

16 . The device of claim 13 , further comprising:
a gate contact in contact with the conical frustum-shaped gate electrode.

17 . The device of claim 16 , further comprising:
a conductive layer in contact with a bottom surface of the conical frustum-shaped gate electrode, the conductive layer has a portion not overlapped with the conical frustum-shaped gate electrode, and the gate contact is further in contact with the portion of the conductive layer.

18 - 20 . (canceled)

21 . A device, comprising:
a conductive layer; a gate electrode over the conductive layer; a doped nanowire through the conductive layer and the gate electrode; and a gate contact having a bottom surface in contact with the conductive layer and a sidewall in contact with the gate electrode, wherein the sidewall of the gate contact is inclined with respect to the bottom surface of the gate contact.

22 . The device of claim 21 , wherein the gate electrode tapers in a direction away from the conductive layer.

23 . The device of claim 21 , wherein the doped nanowire comprises a metal-containing material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yung-Chih
• Liao Yu-Chieh
• Yang Tai-I
• Chen Hsin-Ping

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L29/42376 Primary

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title