Root complex integrated endpoint emulation of a discreet pcie endpoint

Patent metadata

Field	Value
Publication number	US-2019095554-A1
Application number	US-201715718110-A
Country	US
Kind code	A1
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Mar 28, 2019
Grant date	—

Abstract

Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

First claim

What is claimed is:

1 . An apparatus implemented at least partially in hardware, the apparatus comprising hardware logic to:
receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

2 . The apparatus of claim 1 , further comprising logic to:
determine that the request message comprises a read request to read one or more PCIe registers; and wherein the logic responds to the read request by transmitting bit strings without PCIe-specific register values.

3 . The apparatus of claim 1 , further comprising logic to:
determine that the request message comprises a write request to write to one or more PCIe-specific registers; and wherein the logic drops the write request.

4 . The apparatus of claim 1 , further comprising logic to:
receive from an endpoint device a response message responding to the request message; determine that the response message include PCIe-specific information; and modify or drop the PCIe-specific information before transmitting the response message.

5 . The apparatus of claim 1 , further comprising logic to:
receive from an endpoint device a PCIe-specific message; and reroute the PCIe-specific message to an event handler.

6 . The apparatus of claim 5 , wherein the PCIe-specific message comprises a PCIe error message, and the logic is to forward the PCIe error message to a PCIe error handler.

7 . The apparatus of claim 1 , further comprising logic to:
determine that the request message includes a request to access PCIe-specific registers of an endpoint device and a request to access non-PCIe-specific registers of the endpoint device; transmit the request message to access the non-PCIe-specific registers to the endpoint device; and hide the PCIe-specific registers.

8 . The apparatus of claim 1 , wherein the apparatus resides upstream of a PCIe-compliant root complex.

9 . The apparatus of claim 1 , wherein the apparatus resides on a PCIe-compliant endpoint device.

10 . The apparatus of claim 1 , wherein the PCIe-specific registers are registers associated with one or more of a PCIe-compliant root complex, a PCIe-compliant root complex controller, or a PCIe port.

11 . A method performed by an emulation hardware element, the method comprising:
receiving a request message to access one or more registers of a hardware device; determining that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and responding to the request message without providing information associated with the one or more PCIe-specific registers.

12 . The method of claim 11 , further comprising:
determining that the request message comprises a read request to read one or more PCIe registers; and transmitting bit strings without register-specific values.

13 . The method of claim 11 , further comprising:
determining that the request message comprises a write request to write to one or more PCIe registers; and dropping the write request.

14 . The method of claim 11 , further comprising:
receiving from an endpoint device a response message responding to the request message; determining that the response message include PCIe-specific information; and modifying or dropping the PCIe-specific information before transmitting the response message.

15 . The method of claim 11 , further comprising:
receiving from an endpoint device a PCIe-specific message; and rerouting the PCIe-specific message to an event handler.

16 . The method of claim 15 , wherein the PCIe-specific message comprises a PCIe error message, and the method further comprises forwarding the PCIe error message to a PCIe error handler.

17 . The method of claim 11 , further comprising:
determining that the request message includes a request to access PCIe-specific registers of an endpoint device and a request to access non-PCIe-specific registers of the endpoint device; transmitting the request message to access the non-PCIe-specific registers to the endpoint device; and forgo transmitting the request to access the PCIe-specific registers.

18 . The method of claim 11 , further comprising generating a type 0 configuration register access message, the type 0 configuration configured for a discreet endpoint device; and forwarding the type 0 configuration register to the discreet endpoint device across a PCIe-compliant link.

19 . A host system comprising:
a processor running an operating system; a Peripheral Component Interconnect Express (PCIe)-compliant root complex, the PCIe-compliant root complex; and emulation hardware comprising logic to:
receive a register access request message from the operating system;
determine one or more PCIe-specific registers in the request message; and
hide the PCIe-specific registers from the operating system.

20 . The host system of claim 19 , further comprising a PCIe-compliant port, the emulation hardware comprising logic to hide PCIe-specific registers associated with the PCIe-compliant port from the operating system.

21 . The host system of claim 19 , further comprising a PCIe-compliant endpoint device, wherein the emulation hardware comprises logic to hide PCIe-specific registers associated with the PCIe-compliant endpoint device from the operating system.

22 . The host system of claim 19 , wherein the emulation hardware comprises logic to hide PCIe-specific registers based on a type of register access identified from the register access request message.

23 . The host system of claim 22 , wherein the emulation hardware comprises logic to drop write requests to PCIe-specific registers received from the operating system and provide null data in response to read requests to PCIe-specific registers received from the operating system.

24 . The host system of claim 22 , wherein the emulation hardware comprises logic to modify PCIe-specific register information received in response to a register access request message by creating modified register information that is not compliant with a PCIe protocol; and transmit the modified register information to the operating system.

25 . The host system of claim 19 , further comprising a PCIe-compliant event handler implemented at least partially in hardware, and wherein:
the emulation hardware comprises logic to:
receive one or more PCIe-specific messages from a PCIe-compliant connected device; and
reroute the one or more PCIe-specific messages to the PCIe-compliant event handler.

Assignees

• Intel Corp

Inventors

• Ooi Eng Hun
• Lim Su Wei
• Tan Kuan Hua
• Kalluraya Prashanth

Classifications

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F2213/0026

  PCI express · CPC title