Semiconductor package having an electro-magnetic interference shielding or electro-magnetic wave scattering structure

Patent metadata

Field	Value
Publication number	US-2019081009-A1
Application number	US-201816186305-A
Country	US
Kind code	A1
Filing date	Nov 9, 2018
Priority date	Feb 24, 2017
Publication date	Mar 14, 2019
Grant date	—

Abstract

Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate having a bond finger and a ground bond finger disposed over a top surface of the substrate; and a semiconductor chip mounted over the top surface of the substrate such that an active surface of the semiconductor chip faces the top surface of the substrate, wherein the semiconductor chip comprises: a bonding pad disposed over the active surface and electrically coupled to the bond finger, a ground bonding pad electrically coupled to the ground bond finger, and a ground metal pattern to which the ground bonding pad is coupled, the substrate comprising: an external signal line disposed over the top surface of the substrate and having one end coupled to the bond finger; a ground pattern disposed over the top surface of the substrate, extended from an overlap region where the semiconductor chip overlaps with the substrate to an edge of the substrate, and to which the ground bond finger is coupled; a signal via formed within the substrate and electrically coupled to the external signal line; and a ground via formed within the substrate and electrically coupled to the ground pattern; a first external electrode disposed over a bottom surface of the substrate and electrically coupled to the signal via; and a second external electrode disposed over a bottom surface of the substrate and electrically coupled to the ground via, and the bond finger is disposed to overlap the semiconductor chip, wherein the semiconductor chip comprises bumps formed over the bonding pad and the ground bonding pad to couple the bonding pad and the bond finger and to couple the ground bonding pad and the ground bond finger.

2 . The semiconductor package of claim 1 , wherein the entire external signal line overlaps with the semiconductor chip.

3 . The semiconductor package of claim 1 , further comprising:
a first solder resist formed over the top surface of the substrate to expose the bond finger and the ground bond finger; a second solder resist formed over the bottom surface of the substrate to expose the first and the second external electrodes; a sealing member formed over the top surface of the substrate comprising the first solder resist in such a way as to cover the semiconductor chip; and an external coupling member formed over the first and the second external electrodes.

4 . The semiconductor package of claim 1 , wherein there is a plurality of the ground via, the plurality of ground via configured to minimize a number of electromagnetic waves generated from the external signal line from radiating outside the substrate.

5 . The semiconductor package of claim 4 , wherein the plurality of ground via are located at a perimeter of the substrate.

6 . The semiconductor package of claim 5 , wherein the plurality of ground via are arranged in a loop shape around the perimeter of the substrate.

7 . The semiconductor package of claim 4 , wherein the plurality of ground via are located at a predetermined distance away from the perimeter of the substrate.

8 . The semiconductor package of claim 7 , wherein the plurality of ground via are arranged in a loop shape at the predetermined distance away from the perimeter of the substrate.

9 . The semiconductor package of claim 1 , wherein the signal via is disposed the inside of the overlap region.

Assignees

• Sk Hynix Inc

Inventors

• Jung Won Duck
• Lim Sang Joon
• Lim Sung Mook

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title