Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Method for producing wiring structure
US2019080912A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2019080912-A1 |
| Application number | US-201615765528-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 1, 2016 |
| Priority date | Oct 5, 2015 |
| Publication date | Mar 14, 2019 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
Provided is a method for producing a wiring structural body provided with a wiring pattern, the method including a first step of forming an insulating layer on a surface of a silicon substrate along at least a region for forming the wiring pattern, a second step of forming a boron layer on the insulating layer along the region, and a third step of forming a metal layer on the boron layer by plating.
First claim
Opening claim text (preview).
1 : A method for producing a wiring structural body provided with a wiring pattern, comprising: forming an insulating layer on a surface of a silicon substrate along at least a region for forming the wiring pattern; forming a boron layer on the insulating layer along the region; and forming a metal layer on the boron layer by plating. 2 : The method for producing a wiring structural body according to claim 1 , wherein, in forming the boron layer, the boron layer is isotropically formed on the insulating layer by a vapor deposition, and after that, the boron layer is patterned along the region. 3 : The method for producing a wiring structural body according to claim 1 , wherein in forming the metal layer, a nickel layer is formed on the boron layer by plating.
Assignees
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Classifications
characterised by the filling method or the material of the conductive fill · CPC title
of conductive or resistive materials · CPC title
Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title
on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title
Through-vias · CPC title
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Frequently asked questions
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- What does patent US2019080912A1 cover?
- Provided is a method for producing a wiring structural body provided with a wiring pattern, the method including a first step of forming an insulating layer on a surface of a silicon substrate along at least a region for forming the wiring pattern, a second step of forming a boron layer on the insulating layer along the region, and a third step of forming a metal layer on the boron layer by pla…
- Who is the assignee on this patent?
- Hamamatsu Photonics Kk
- What technology area does this patent fall under?
- Primary CPC classification H10W20/023. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Mar 14 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).