Non volatile memory module for rack implementations

Patent metadata

Field	Value
Publication number	US-2019042511-A1
Application number	US-201816023047-A
Country	US
Kind code	A1
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Feb 7, 2019
Grant date	—

Abstract

An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

First claim

1 . An apparatus, comprising:
a non volatile memory module for insertion into a rack implemented modular computer, the non volatile memory module comprising: a plurality of memory controllers; respective non-volatile random access memory coupled to each of the memory controllers; a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers, the incoming requests sent by one or more CPU modules of the rack implemented modular computer, the outgoing responses sent to the one or more CPU modules.

2 . The apparatus of claim 1 wherein the respective non volatile random access memory is to be assigned system memory address space of the rack implemented modular computer.

3 . The apparatus of claim 1 wherein the switch circuit further comprises a first switch plane to circuit switch the incoming requests and a second switch plane to circuit switch the outgoing responses.

4 . The apparatus of claim 3 wherein the switch circuit further includes incoming request control logic to setup and teardown connections within the switch that transport the incoming requests and outgoing response control logic to setup and teardown connections within the switch that transport the outgoing responses.

5 . The apparatus of 1 wherein the incoming requests are memory access instructions of program code executed by the one or more CPU modules of the rack implemented modular computer.

6 . The apparatus of claim 1 wherein the non modular memory module further comprises queuing circuitry between the rack's backplane and inputs to the switch circuit that receive the incoming requests.

7 . The apparatus of claim 1 wherein the memory controllers further comprise respective incoming request and outgoing response queues.

8 . The apparatus of claim 1 wherein the non-volatile random access memory is composed of three-dimensionally stacked storage cells.

9 . A modular computer, comprising:
a rack; one or more CPU modules that are plugged into the rack, the CPU modules to execute the program code of the modular computer; a non volatile memory module plugged into the rack, the non volatile memory module comprising: a plurality of memory controllers; respective non volatile random access memory coupled to each of the memory controllers; a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers, the incoming requests sent by the one or more CPU modules of the rack implemented modular computer, the outgoing responses sent to the one or more CPU modules.

10 . The modular computer of claim 9 wherein the respective non volatile random access memory is to be assigned system memory address space of the rack implemented modular computer.

11 . The modular computer of claim 9 wherein the switch circuit further comprises a first switch plane to circuit switch the incoming requests and a second switch plane to circuit switch the outgoing responses.

12 . The modular computer of claim 11 wherein the switch circuit further includes incoming request control logic to setup and teardown connections within the switch that transport the incoming requests and outgoing response control logic to setup and teardown connections within the switch that transport the outgoing responses.

13 . The modular computer of 9 wherein the incoming requests are memory access instructions of program code executed by the one or more CPU modules of the rack implemented modular computer.

14 . The modular computer of claim 9 wherein the non modular memory module further comprises queuing circuitry between the rack's backplane and inputs to the switch circuit that receive the incoming requests.

15 . The modular computer of claim 9 wherein the memory controllers further comprise respective incoming request and outgoing response queues.

16 . The modular computer of claim 9 wherein the non volatile random access memory is composed of three-dimensionally stacked storage cells.

17 . A method, comprising:
receiving a memory access read or write request from a backplane of a rack; setting up a first circuit switched connection over a first switch plane for the request, the connection connecting an input of the first switch plane that the request was received at and an output of the first switch plane switch that is coupled to a memory controller, the memory controller coupled to non volatile memory having allocated system memory address space that is targeted by the request; transporting the request over the first circuit switched connection; setting up a second circuit switched connection over a second switch plane for the request's response, the second circuit switched connection connecting an input of the second switch plane that is coupled to the memory controller and an output of the second switch plane that is coupled to the backplane; and, transporting the response over the second circuit switched connection.

18 . The method of claim 17 further comprising tearing down the first circuit switched connection after the transportation of the request over the first circuit switched connection.

19 . The method of claim 17 further comprising tearing down the second circuit switched connection after transportation of the response over the second circuit switched connection.

20 . The method of claim 17 wherein the request is from a memory access instruction being executed by a CPU module that is also plugged into the rack.

21 . An apparatus, comprising:
a memory module for insertion into a rack implemented modular computer, the memory module comprising: a plurality of memory controllers; respective random access memory coupled to each of the memory controllers; a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers, the incoming requests sent by one or more CPU modules of the rack implemented modular computer, the outgoing responses sent to the one or more CPU modules.

Assignees

• Intel Corp

Inventors

• Nachimuthu Murugasamy K
• Schmisseur Mark A
• Ziakas Dimitrios
• Das Sharma Debendra
• Kumar Mohan J

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F3/0607

  by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title