Method for manufacturing semiconductor element of polygon shape

US2019035973A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019035973-A1
Application numberUS-201816149898-A
CountryUS
Kind codeA1
Filing dateOct 2, 2018
Priority dateJun 30, 2015
Publication dateJan 31, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer to separate the semiconductor wafer at the cleavage starting portion. The pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for manufacturing a semiconductor element, comprising: providing a receiving plate defining a recess, an adhesive sheet fixed to the receiving plate and spaced apart from a surface of the recess, and a semiconductor wafer fixed to the adhesive sheet, the semiconductor water including a substrate, a semiconductor structure on a first surface of the substrate, electrodes and a cleavage starting portion in the substrate; and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on a second surface of the semiconductor wafer opposite to the first surface in a state where the semiconductor wafer is pressed toward the surface of the recess, thereby the semiconductor wafer is separated at the cleavage starting portion, wherein the pressing member includes a tip portion to be pressed on the semiconductor wafer, and the tip portion has a spherical surface or a curved surface. 2 . The method for manufacturing the semiconductor element according to claim 1 , wherein, in the providing the receiving plate, the adhesive sheet and the semiconductor wafer, the semiconductor wafer is arranged above the recess. 3 . The method for manufacturing the semiconductor element according to claim 1 , wherein inside the recess is hollow. 4 . The method for manufacturing the semiconductor element according to claim 1 , wherein, in the dividing the semiconductor wafer into the semiconductor elements, the semiconductor wafer is separated without being pressed against the surface of the receiving plate. 5 . The method for manufacturing the semiconductor element according to claim 1 , wherein the cleavage starting portion is formed by focusing a laser beam in an interior of the substrate. 6 . The method for manufacturing the semiconductor element according to claim 1 , wherein the substrate has a crystal structure of a hexagonal crystal system, and the shape of each semiconductor element in the plan view is a hexagon. 7 . The method for manufacturing the semiconductor element according to claim 1 , wherein each of the plurality of semiconductor elements has a shape of a polygon having five or more angles in a plan view. 8 . The method for manufacturing the semiconductor element according to claim 7 , wherein the dividing the semiconductor wafer into the semiconductor elements comprises scanning the pressing member on the semiconductor wafer in a direction that is not parallel to any side forming an outer shape of the polygon of each semiconductor element in the plan view. 9 . The method for manufacturing the semiconductor element according to claim 8 , wherein the dividing the semiconductor wafer into the semiconductor elements comprises scanning the pressing member linearly. 10 . The method for manufacturing the semiconductor element according to claim 7 , wherein the dividing the semiconductor wafer into the semiconductor elements comprises scanning the pressing member on the semiconductor wafer in a direction inclined with respect to an orientation flat surface of the semiconductor wafer in the plan view. 11 . The method for manufacturing the semiconductor element according to claim 7 , wherein an outer shape of the tip portion is longer than a diameter of a circumscribed circle of the shape of the semiconductor element in the plan view. 12 . The method for manufacturing the semiconductor element according to claim 11 , wherein the outer shape of the tip portion is two times or more as long as the diameter of the circumscribed circle of the shape of the semiconductor element in the plan view. 13 . The method for manufacturing the semiconductor element according to claim 1 , wherein, before the dividing the semiconductor wafer into the semiconductor elements, the cleavage starting portion reaches the second surface of the semiconductor wafer. 14 . The method for manufacturing the semiconductor element according to claim 7 , wherein the cleavage starting portion is formed in a bent polygonal line in the plan view.

Assignees

Inventors

Classifications

  • used during dicing or grinding · CPC title

  • using temporarily an auxiliary support · CPC title

  • Cutting or separating of wafers, substrates or parts of devices · CPC title

  • Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US2019035973A1 cover?
A method for manufacturing a semiconductor element is provided. The method includes providing a semiconductor wafer including a substrate and a semiconductor structure on the substrate, forming a cleavage starting portion in the semiconductor wafer, and dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a s…
Who is the assignee on this patent?
Nichia Corp
What technology area does this patent fall under?
Primary CPC classification H01L33/0095. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 31 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).