Semiconductor device

Patent metadata

Field	Value
Publication number	US-2019035776-A1
Application number	US-201816150913-A
Country	US
Kind code	A1
Filing date	Oct 3, 2018
Priority date	Mar 17, 2000
Publication date	Jan 31, 2019
Grant date	—

Abstract

A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level; a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, wherein the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein: the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction, the plurality of dummy wirings having: a first dummy wiring; a second dummy wiring; and a third dummy wiring, wherein centers of the second dummy wiring and the third dummy wiring are nearest to a center of the first dummy wiring relative to others of the plurality of dummy wirings, and the respective centers of the first dummy wiring, the second dummy wiring, and the third dummy wiring are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first direction and the second direction.

2 . The semiconductor device according to claim 1 ,
the plurality of dummy wirings having: a fourth dummy wiring; a fifth dummy wiring, wherein centers of the fourth dummy wiring and the fifth dummy wiring are nearest to a center of the first dummy wiring relative to other of the plurality of dummy wirings; wherein respective centers of the first dummy wiring, the fourth dummy wiring, and the fifth dummy wiring are aligned on a fourth virtual linear line extending in a sixth direction neither parallel to nor perpendicular to the first direction and the second direction.

3 . The semiconductor device according to claim 2 , wherein an angle between the third virtual linear line and the first direction is the same as an angle between the fourth virtual linear line and the second direction, and
the plurality of dummy wirings have rotational symmetries through 90 degrees about respective centers of the plurality of the dummy wirings.

4 . The semiconductor device according to claim 1 , wherein an angle between the third virtual linear line and the first direction is between 2 and 40°, or an angle between the fourth virtual linear line and the first direction is between 2 and 40°.

5 . The semiconductor device according to claim 1 , wherein the plurality of dummy wirings are square-shaped in a plan view, and a dummy wiring nearest to the first wiring or the second wiring has the same shape as the adjacent dummy wirings.

6 . The semiconductor device according to claim 5 , wherein an angle between the third virtual linear line and the first direction is between 15 and 25°, or an angle between the fourth virtual linear line and the first direction is between 15 and 25°, and
an angle between the third virtual linear line and the fourth virtual linear line is 90°.

7 . The semiconductor device according to claim 5 , wherein an angle between the third virtual linear line and the first direction is between 2 and 40°, and an angle between the fourth virtual linear line and the second direction is between 2 and 40°.

8 . The semiconductor device according to claim 4 , wherein a length of a side of each of the plurality of dummy wirings is in a range of 1 to 10 μm.

9 . The semiconductor device according to claim 4 , wherein a length of a side of each of the plurality of dummy wirings is in a range of 1 to 10 μm, and
at least one of a distance between the plurality of first wirings and the nearest one of the plurality of dummy wirings and a distance between the second wiring and the nearest one of the plurality of dummy wirings is in a range of 0.5 to 20.0 μm.

10 . The semiconductor device of according to claim 4 , wherein a length of a side of each of the plurality of dummy wirings is in a range of 1 to 10 μm,
each distance between adjacent ones of the plurality of dummy wirings is about half of a length of each side of each of the plurality of dummy wirings, and
at least one of a distance between the plurality of first wirings and the nearest one of the plurality of dummy wirings and a distance between the second wiring and the nearest one of the plurality of dummy wirings is in a range of 0.5 to 20.0 μm.

11 . The semiconductor device according to claim 1 , wherein the plurality of dummy wirings are square-shaped in a plan view, and
closest distances between the second wiring and the nearest one of the plurality of dummy wirings are different from each other.

12 . The semiconductor device according to claim 1 ,
wherein each of the plurality of dummy wirings has a first side, a second side parallel to the first side, a third side perpendicular to the first side, and a fourth side parallel to the third side, each length of the first side, the second side, the third side, and the fourth side is in a range of 1 to 10 μm, and each distance between adjacent sides of the plurality of dummy wirings is in a range of 0.5 to 5.0 μm.

13 . The semiconductor device according to claim 4 ,
wherein the plurality of dummy wirings are square-shaped in a plan view, a length of a side of each of the plurality of dummy wirings is in a range of 1 to 10 μm, each distance between adjacent ones of the plurality of dummy wirings is in a range of 0.5 to 5.0 μm, and an angle between the first virtual linear line and the second virtual linear line is 90°.

14 . The semiconductor device according to claim 13 ,
wherein a side of each of the plurality of dummy wirings is in a range of 1 to 10 μm, each space between adjacent ones of the plurality of dummy wirings is in a range of 0.5 to 5.0 μm, an angle between the first virtual linear line and the second virtual linear line is 90°, and a space between the second wiring and the nearest one of the plurality of dummy wirings is in a range of 0.5 to 20.0 μm.

15 . The semiconductor device according to claim 13 , further comprising:
a via plug connecting a wiring on another layer level and a third wiring on the layer level.

16 . The semiconductor device according to claim 15 ,
wherein the plug is made of tungsten.

17 . The semiconductor device according to claim 1 ,
wherein a dummy wiring of the plurality of dummy wirings nearest to the second wiring has the same shape as the adjacent dummy wirings of the plurality of dummy wirings.

18 . The semiconductor device according to claim 4 , further comprising:
a via plug connecting a wiring on another layer level and a third wiring on the layer level, and wherein an angle between the third virtual linear line and the fourth virtual linear line is 90°.

19 . The semiconductor device according to claim 18 ,
wherein the plug is made of tungsten.

Assignees

• Seiko Epson Corp

Inventors

• Mori Katsumi
• Kawahara Kei
• Kasuya Yoshikazu

Classifications

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title