Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2019013357-A1
Application number	US-201816018333-A
Country	US
Kind code	A1
Filing date	Jun 26, 2018
Priority date	Jul 6, 2017
Publication date	Jan 10, 2019
Grant date	—

Abstract

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first memory cell extending in a first direction and including a first phase change memory and a first ovonic threshold switch (OTS) on the first phase change memory; a second memory cell extending in the first direction and including a second phase change memory and a second OTS on the second phase change memory, the second memory cell spaced apart from the first memory cell in a second direction intersecting the first direction; a first capping film on side surfaces of the first and second memory cells; and a second capping film on the first capping film and filling a space between the first and second memory cells.

2 . The semiconductor device as claimed in claim 1 , wherein:
the first memory cell includes a first upper electrode on the first OTS and a first lower electrode below the first phase change memory, and the second memory cell includes a second upper electrode on the second OTS and a second lower electrode below the second phase change memory.

3 . The semiconductor device as claimed in claim 2 , wherein:
the first memory cell includes a first intermediate electrode between the first OTS and the first phase change memory, and the second memory cell includes a second intermediate electrode between the second OTS and the second phase change memory.

4 . The semiconductor device as claimed in claim 1 , wherein an aspect ratio of the first and second memory cells is 5 or more.

5 . The semiconductor device as claimed in claim 1 , wherein the first and second capping films include different materials.

6 . The semiconductor device as claimed in claim 1 , wherein a wet etch rate (WER) of the first capping film with respect to HF is greater than a wet etch rate of the second capping film with respect to HF.

7 . The semiconductor device as claimed in claim 1 , wherein each of the first and second capping films includes at least one of SiN, SiON, SiCN, and SiBN.

8 . A semiconductor device, comprising:
a first word line extending in a first direction; a first bit line extending in a second direction intersecting the first direction, the first bit line spaced apart from the first word line in a third direction intersecting the first and second directions; a first memory cell extending in the third direction between the first word line and the first bit line, the first memory cell including a first phase change memory and a first OTS which are sequentially stacked, a first capping film surrounding a side surface of the first memory cell; and a second capping film on an outer side surface of the first capping film and filling a space between the first bit line and the first word line.

9 . The semiconductor device as claimed in claim 8 , wherein a wet etch rate (WER) of the first capping film with respect to HF is greater than a wet etch rate of the second capping film with respect to HF.

10 . The semiconductor device as claimed in claim 8 , wherein the first memory cell includes a first lower electrode below the first phase change memory.

11 . The semiconductor device as claimed in claim 10 , further comprising:
a mold film surrounding the first lower electrode, wherein the first and second capping films are on the mold film.

12 . The semiconductor device as claimed in claim 11 , further comprising:
a second bit line extending in the second direction, spaced apart from the first bit line in the first direction, and spaced apart from the first word line in the third direction; and a second memory cell in the third direction between the second bit line and the first word line, the second memory cell including a second phase change memory and a second OTS which are sequentially stacked.

13 . The semiconductor device as claimed in claim 12 , wherein the first capping film includes:
a first portion surrounding a side surface of the first memory cell, a second portion surrounding a side surface of the second memory cell, and a third portion along an upper surface of the mold film.

14 . The semiconductor device as claimed in claim 12 , wherein the first lower electrode includes:
a first part below the first phase change memory of the first memory cell, a second part below the second phase change memory of the second memory cell, and a third part connecting the first part to the second part.

15 . A semiconductor device, comprising:
a first word line extending in a first direction; a second word line on the first word line, the second word line extending in the first direction; a first bit line extending in a second direction intersecting the first direction, the first bit line being between the first and second word lines; a first memory cell in a vertical direction between the first word line and the first bit line, the first memory cell including a first phase change memory and a first OTS which are sequentially stacked; a second memory cell in the vertical direction between the second word line and the first bit line, the second memory cell including a second phase change memory and a second OTS which are sequentially stacked; a first capping film surrounding a side surface of the first memory cell; a second capping film surrounding a side surface of the second memory cell; a third capping film on the first capping film to fill a space between the first bit line and the first word line; and a fourth capping film on the second capping film to fill a space between the first bit line and the second word line.

16 . The semiconductor device as claimed in claim 15 , wherein:
a wet etch rate of the first capping film with respect to HF is greater than a wet etch rate of the third capping film with respect to HF, and a wet etch rate of the second capping film with respect to HF is greater than a wet etch rate of the fourth capping film with respect to HF.

17 . The semiconductor device as claimed in claim 15 , further comprising:
a second bit line extending in the second direction, the second bit line being between the first and second word lines and spaced apart from the first bit line in the first direction; and a third memory cell in the vertical direction between the first word line and the second bit line, the third memory cell including a third phase change memory and a third OTS which are sequentially stacked.

18 . The semiconductor device as claimed in claim 17 , further comprising:
a first lower electrode below the first and third phase change memories and shared by the first and third memory cells.

19 . The semiconductor device as claimed in claim 15 , wherein:
the first and second capping films include different materials from each other, and the second and fourth capping films include different materials from each other.

20 . The semiconductor device as claimed in claim 15 , wherein an aspect ratio of the first and second memory cells is 5 or more.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Uk
• Park Jeong Hee
• Park Seong Geon
• Park Soon Oh
• Lee Jung Moo

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C13/003

  Cell access · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title