Integrated circuit devices with selectively arranged through substrate vias and method of manufacture thereof
US-2018182717-A1 · Jun 28, 2018 · US
Semiconductor device
US2018374768A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018374768-A1 |
| Application number | US-201816009753-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 15, 2018 |
| Priority date | Jun 22, 2017 |
| Publication date | Dec 27, 2018 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor device according to an embodiment includes a semiconductor chip including a region having through holes; a substrate having a first opening larger than the region, the substrate containing a resin or a ceramic; a spacer provided between the semiconductor chip and the substrate, the spacer having a second opening larger than the region; a first bond provided between the semiconductor chip and the spacer; and a second bond provided between the spacer and the substrate.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device comprising: a semiconductor chip including a region having through holes; a substrate having a first opening larger than the region, the substrate containing a resin or a ceramic; a spacer provided between the semiconductor chip and the substrate, the spacer having a second opening larger than the region; a first bond provided between the semiconductor chip and the spacer; and a second bond provided between the spacer and the substrate. 2 . The semiconductor device according to claim 1 , wherein a thermal expansion coefficient of the spacer is smaller than a thermal expansion coefficient of the substrate. 3 . The semiconductor device according to claim 1 , wherein a thickness of the spacer is larger than a thickness of the semiconductor chip. 4 . The semiconductor device according to claim 1 , wherein a gap exists between the spacer and the semiconductor chip. 5 . The semiconductor device according to claim 1 , wherein the first bond is consists of a plurality of portions. 6 . The semiconductor device according to claim 1 , wherein a thickness of the first bond is 5 μm or more. 7 . The semiconductor device according to claim 1 , wherein the semiconductor chip includes pairs of electrodes and wiring layers, each of the through holes interposed between each of the pairs of electrodes, and each of the wiring layers connected to each of the pairs of electrodes, respectively. 8 . The semiconductor device according to claim 1 , wherein the second opening is smaller than the first opening. 9 . The semiconductor device according to claim 1 , wherein a surface of the spacer is covered with a conductive material. 10 . The semiconductor device according to claim 1 , wherein the semiconductor chip includes a first electrode pad, the substrate includes a second electrode pad, and further including a bonding wire electrically connecting the first electrode pad and the second electrode pad. 11 . The semiconductor device according to claim 1 , wherein the semiconductor chip includes a silicon layer. 12 . The semiconductor device according to claim 1 , wherein the spacer includes a semiconductor or an insulator. 13 . The semiconductor device according to claim 1 , wherein the substrate is a printed board. 14 . The semiconductor device according to claim 1 , wherein a ratio of a thickness of the spacer to a thickness of the semiconductor chip is 5 or more and 50 or less. 15 . The semiconductor device according to claim 1 , wherein a curing temperature of the first bond and the second bond is 200° C. or less.
Assignees
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Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
comprising gold [Au] · CPC title
- H10W70/68Primary
Shapes or dispositions thereof · CPC title
Organic materials · CPC title
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Frequently asked questions
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- What does patent US2018374768A1 cover?
- A semiconductor device according to an embodiment includes a semiconductor chip including a region having through holes; a substrate having a first opening larger than the region, the substrate containing a resin or a ceramic; a spacer provided between the semiconductor chip and the substrate, the spacer having a second opening larger than the region; a first bond provided between the semicondu…
- Who is the assignee on this patent?
- Nuflare Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W70/68. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Dec 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).