Serial memory interface circuitry for programmable integrated circuits

Patent metadata

Field	Value
Publication number	US-9712186-B1
Application number	US-201414256407-A
Country	US
Kind code	B1
Filing date	Apr 18, 2014
Priority date	Apr 18, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

First claim

What is claimed is:

1. A programmable integrated circuit that communicates with an external memory over a serial communications path, the programmable integrated circuit comprising:
user logic formed from programmable logic on the programmable integrated circuit; and
memory interface circuitry that serves as an interface between the user logic and the serial communications path, wherein the memory interface circuitry includes a soft memory interface circuit formed from the programmable logic and a hardwired memory interface circuit having at least one predefined function.

2. The programmable integrated circuit defined in claim 1 wherein the soft memory interface circuit includes a packet formation circuit that forms outgoing packets with empty fields.

3. The programmable integrated circuit defined in claim 2 wherein the hardwired memory interface circuit includes substitution logic that inserts information into the empty fields.

4. The programmable integrated circuit defined in claim 3 wherein the substitution logic substitutes information into the empty fields that is selected from the group consisting of: sequence number information, cyclic redundancy check information, and acknowledgement information.

5. The programmable integrated circuit defined in claim 3 wherein the empty fields include an empty sequence number field and wherein the substitution logic substitutes a sequence number into the empty sequence number field based on sequence number information.

6. The programmable integrated circuit defined in claim 5 wherein the hardwired memory interface circuit includes a retransmission buffer that provides the sequence number information to the substitution logic.

7. The programmable integrated circuit defined in claim 3 wherein the empty fields include an empty acknowledgement field, wherein the hardwired memory interface circuitry includes a sequence number extractor that extracts sequence number information from incoming packets from the external memory and that provides a received sequence number to the substitution logic, wherein the substitution logic uses the received sequence number to substitute an acknowledgment into the empty acknowledgment field, wherein the empty fields include an empty cyclic redundancy check field, wherein the hardwired memory interface circuit includes a cyclic redundancy check generator that inserts a cyclic redundancy check value into the empty cyclic redundancy check field, wherein the programmable integrated circuit further comprises registers that store information on locations for the empty fields within the outgoing packets, wherein the sequence number extractor provides received acknowledgement information to the retransmission buffer, and wherein the retransmission buffer is configured to clear stored packets based on the received acknowledgement information.

8. The programmable integrated circuit defined in claim 1 wherein the hardwired memory interface circuitry includes lane bonding circuitry and serializer-deserializer circuitry coupled to the serial communications path.

9. The programmable integrated circuit defined in claim 1 wherein the hardwired memory interface circuit has a plurality of predefined functions, the programmable integrated circuit further comprising circuitry that supplies at least one control signal to the hardwired circuitry to select a given predefined function from the plurality of predefined functions.

10. Memory interface circuitry that serves as an interface between a logic circuit and a memory that is coupled to the memory interface by a serial communications path, comprising:
packet formation logic formed from programmable logic, wherein the packet formation logic forms data packets with empty fields;
a hardwired substitution logic circuit that inserts information into the empty fields; and
hardwired logic that extracts information from at least one field in data packets received from the memory.

11. The memory interface circuitry defined in claim 10 wherein the information that is extracted by the hardwired logic includes information selected from the group consisting of: a cyclic redundancy check, an acknowledgement, and a sequence number.

12. The memory interface circuitry defined in claim 11 wherein the information extracted by the hardwired logic is the acknowledgement.

13. The memory interface circuitry defined in claim 11 wherein the information extracted by the hardwired logic is the sequence number.

14. The memory interface circuitry defined in claim 11 wherein the information extracted by the hardwired logic is the cyclic redundancy check.

15. The memory interface circuitry defined in claim 14 further comprising a hardwired cyclic redundancy checker circuit that performs cyclic redundancy checking on the cyclic redundancy check extracted from the data packets received from the memory.

16. The memory interface circuitry defined in claim 10 further comprising a hardwired cyclic redundancy checker circuit that provides the packets received from the memory to a sequence number extractor and is configured to assert a flag to inform the sequence number extractor when received packets are free of errors.

17. The memory interface circuitry defined in claim 10 further comprising registers that provide the hardwired substitution logic circuit with information identifying where the empty fields are located within the packets.

18. A method of processing packets with a memory interface circuit on a programmable integrated circuit that is coupled to an external memory over a serial communications path, the method comprising:
with packet formation logic in the memory interface circuit that is implemented in programmable logic, forming outgoing packets for the external memory that include empty fields; and
with a hardwired logic circuit in the memory interface circuit, inserting information in one of the empty fields, wherein the information is selected from the group consisting of: a packet acknowledgement, a sequence number, and a cyclic redundancy check.

19. The method defined in claim 18 further comprising:
with a hardwired sequence number extractor, extracting sequence numbers from packets received from the external memory and providing the extracted sequence numbers to the hardwired logic circuit.

20. A method of processing packets with a memory interface circuit on a programmable integrated circuit that is coupled to an external memory over a serial communications path, the method comprising:
with packet formation logic in the memory interface circuit that is implemented in programmable logic, forming outgoing packets for the external memory that include empty fields; and
with a hardwired logic circuit in the memory interface circuit, inserting information into the empty fields.

21. The method defined in claim 20 wherein inserting the information comprises inserting packet acknowledgement information.

22. The method defined in claim 21 wherein inserting the acknowledgement information comprises inserting a return retry pointer.

23. The method defined in claim 20 wherein inserting the information comprises inserting sequence number information.

24. The method defined in claim 23 wherein inserting the sequence number information comprises inserting a forward retry pointer, a sequence number, and a tag field.

25. The method defined in claim 20 wherein inserting the information comprises inserting cyclic redundancy check inf

Assignees

• Altera Corp

Inventors

• Schulz Jeffrey

Classifications

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H04L1/1607

  Details of the supervisory signal · CPC title

• H04L1/0078 Primary

  Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location (forward error control, e.g. FEC, CRC H04L1/004; adaptive formatting H04L1/0006; mappings H04L27/00) · CPC title

• H04L1/1829

  Arrangements specially adapted for the receiver end · CPC title

• H03M13/093 Primary

  CRC update after modification of the information word · CPC title