Method for Manufacturing Magnetic Memory Cells

Patent metadata

Field	Value
Publication number	US-2018366642-A1
Application number	US-201816112173-A
Country	US
Kind code	A1
Filing date	Aug 24, 2018
Priority date	Jun 9, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a selector film stack on a substrate; depositing a magnetic memory element film stack on top of the selector film stack; etching the magnetic memory element film stack with an etch mask formed thereon to remove at least an insulating tunnel junction layer in the magnetic memory element film stack not covered by the etch mask, thereby forming a magnetic memory element pillar; depositing a first conforming dielectric layer over the magnetic memory element pillar, including a sidewall thereof, and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the insulating tunnel junction layer of the magnetic memory element pillar; and etching the selector film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

First claim

1 . A method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a selection element comprising a two-terminal selector, the method comprising the steps of:
depositing a selector film stack for the two-terminal selector on a substrate; depositing a magnetic memory element film stack for the magnetic memory element on top of the selector film stack, the magnetic memory element film stack including a magnetic reference layer film and a magnetic free layer film with an insulating tunnel junction layer film interposed therebetween; etching the magnetic memory element film stack with an etch mask formed thereon to remove at least a first portion of the insulating tunnel junction layer film not covered by the etch mask to form a magnetic memory element pillar that includes a second portion of the insulating tunnel junction layer film; depositing a first conforming dielectric layer over the magnetic memory element pillar, including a sidewall thereof, and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the second portion of the insulating tunnel junction layer film of the magnetic memory element pillar; and etching the selector film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

2 . The method of claim 1 , wherein the substrate includes therein a conductive line electrically connected to the memory cell pillar, the conductive line extending along a direction parallel to a substrate surface.

3 . The method of claim 1 , wherein the substrate includes a via embedded in a dielectric matrix, the via being connected to the memory cell pillar above and a conductive line below, the conductive line extending along a direction parallel to a substrate surface.

4 . The method of claim 3 , wherein top of the via is fully covered by the memory cell pillar.

5 . The method of claim 1 , wherein the first protective sleeve is made of a compound comprising silicon and nitrogen.

6 . The method of claim 1 , wherein all layers of the magnetic memory element film stack not covered by the etch mask are removed during the step of etching the magnetic memory element film stack.

7 . The method of claim 1 , further comprising the step of depositing a second conforming dielectric layer over the memory cell pillar and the first protective sleeve to form a second protective sleeve.

8 . The method of claim 7 , wherein the second protective sleeve is made of a compound comprising silicon and nitrogen.

9 . The method of claim 7 , wherein the second protective sleeve is made of an oxide.

10 . The method of claim 7 , further comprising the step of forming an interlayer dielectric layer surrounding the second protective sleeve.

11 . The method of claim 7 , further comprising the step of forming a conductive line connected to the memory cell pillar from above, the conductive line extending along a direction parallel to a substrate surface.

Assignees

• Avalanche Technology Inc

Inventors

• Yang Hongxin
• Jung Dong Ha
• Zhang Jing
• Yen Bing K

Classifications

• H01L43/08

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/224

  Electricity · mapped topic

• H10B61/10

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title