Method of manufacturing power semiconductor device

Patent metadata

Field	Value
Publication number	US-2018358451-A1
Application number	US-201816106622-A
Country	US
Kind code	A1
Filing date	Aug 21, 2018
Priority date	Mar 10, 2017
Publication date	Dec 13, 2018
Grant date	—

Abstract

A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.

First claim

What is claimed is:

1 . A power semiconductor device, comprising:
trenches in a substrate, wherein the substrate comprises a first surface and a second surface opposite to the first surface; a gate insulating layer and a gate electrode in each of the trenches; a P-type base region between the trenches in the substrate; an N+ source region in the substrate; a P+ doped region on the P-type base region; an interlayer insulating layer on the N+ source region; and an emitter electrode in contact with the N+ source region and the P+ doped region, wherein the N+ source region and the P+ doped region each contact a vertical sidewall of the emitter electrode.

2 . The power semiconductor device of claim 1 , further comprising:
a floating region in the substrate, wherein the floating region has a depth deeper than a depth of the P-type base region.

3 . The power semiconductor device of claim 1 , wherein the substrate comprises a high-concentration first epitaxial-layer and a low-concentration second epitaxial-layer.

4 . The power semiconductor device of claim 1 , wherein the P+ doped region has a greater depth than a depth of the N+ source region.

5 . The power semiconductor device of claim 1 , wherein the interlayer insulating layer comprises two stacked layers.

6 . The power semiconductor device of claim 5 , wherein a first layer of the interlayer insulating layer is a Chemical Vapor Deposition (CVD) oxide layer, and a second layer of the interlayer insulating layer is one of phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG).

7 . The power semiconductor device of claim 1 , further comprising:
a P-type collector region on the second surface of the substrate; and a drain electrode on the P-type collector region.

8 . The power semiconductor device of claim 1 , wherein a portion of the P+ doped region contacting a vertical sidewall of the emitter electrode is larger than a portion of the N+ source region contacting the vertical sidewall of the emitter electrode.

9 . A power semiconductor device, comprising:
trenches in a substrate comprising a first surface and a second surface opposite to the first surface; a gate insulating layer and a gate electrode in each of the trenches; a P-type base region in the substrate; a P+ doped region and an N+ source region in the P-type base region; an interlayer insulating layer on the P+ doped region and the N+ source region; and an emitter electrode contacting the N+ source region, wherein a portion of the P+ doped region contacts both a vertical sidewall of the emitter electrode and a bottom surface of the emitter electrode.

10 . The power semiconductor device of claim 9 , wherein a portion of the N+ source region contacts a vertical sidewall of the emitter electrode.

11 . The power semiconductor device of claim 10 , wherein the portion of the P+ doped region contacting a vertical sidewall of the emitter electrode is larger than the portion of the N+ source region contacting the vertical sidewall of the emitter electrode.

12 . The power semiconductor device of claim 9 , further comprising:
a collector region on the second surface of the substrate; and a drain electrode on the collector region.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Park Jeong Hwan
• Park Seung Sik
• Yang Ha Yong

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/6923

  the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG · CPC title