Electronic devices formed in a cavity between substrates and including a via
US-2018159503-A1 · Jun 7, 2018 · US
Wafer level package and manufacturing method thereof
US2018358305A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018358305-A1 |
| Application number | US-201815992376-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 30, 2018 |
| Priority date | Jun 8, 2017 |
| Publication date | Dec 13, 2018 |
| Grant date | — |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
A wafer level package includes: a substrate having a circuit pattern unit, a pad spaced apart from the circuit pattern unit, a bonding pad disposed on a side of the pad, and a first protection dam; and a printed circuit board having a connection pad and a second protection dam, where the substrate and the printed circuit board are attached through the bonding and connection pads and the first and second protection dams. A method of manufacturing a wafer level package includes: forming a circuit pattern unit on a substrate; disposing a pad spaced apart from the circuit pattern unit; forming a secondary film on a side of the pad; forming a protection film, excluding some of the pads where the secondary film is formed; disposing a bonding pad and a protection dam on a side of the pad; attaching the manufactured substrate and printed circuit board to each other.
First claim
Opening claim text (preview).
What is claimed is: 1 . A wafer level package comprising: a substrate having a circuit pattern unit, a pad formed to be spaced apart from the circuit pattern unit, a bonding pad disposed on a side of the pad, and a first protection dam; and a printed circuit board having a connection pad and a second protection dam, wherein the substrate and the printed circuit board are attached through the bonding pad, the connection pad, the first protection dam and the second protection dam. 2 . The package according to claim 1 , wherein the bonding pad is configured of conductive materials of single layer or multiple layers. 3 . The package according to claim 1 , wherein the first protection dam has conductive materials and a structure the same as those of the bonding pad. 4 . The package according to claim 1 , wherein the bonding pad and the connection pad, and the first protection dam and the second protection dam are attached to configure a Cu—Sn—Cu or Au—Sn—Au structure overall. 5 . The package according to claim 4 , wherein when the bonding pad and the connection pad, and the first protection dam and the second protection dam are attached to configure a Cu—Sn—Cu structure overall, the connection pad and the second protection dam are configured as a Cu single layer structure if the bonding pad and the first protection dam are a Cu—Sn stack structure, and the connection pad and the second protection dam are configured as a Sn—Cu stack structure if the bonding pad and the first protection dam are a Cu single layer structure. 6 . The package according to claim 4 , wherein when the bonding pad and the connection pad, and the first protection dam and the second protection dam are attached to configure an Au—Sn—Au structure overall, the connection pad and the second protection dam are configured as an Au single layer structure if the bonding pad and the first protection dam are an Au—Sn stack structure, and the connection pad and the second protection dam are configured as an Sn—Au stack structure if the bonding pad and the first protection dam are an Au single layer structure. 7 . The package according to claim 1 , wherein the circuit pattern unit is an IDT electrode unit. 8 . A method of manufacturing a wafer level package, the method comprising the steps of: forming a circuit pattern unit on a substrate; disposing a pad to be spaced apart from the circuit pattern unit; forming a secondary film on a side of the pad; forming a protection film, excluding some of the pads on which the secondary film is formed; disposing a bonding pad and a protection dam on a side of the pad; and attaching the manufactured substrate and printed circuit board to each other, wherein the substrate is simply manufactured compared with a plating method. 9 . The method according to claim 8 , wherein the bonding pad is configured of conductive materials of single layer or multiple layers. 10 . The method according to claim 8 , wherein the first protection dam has conductive materials and a structure the same as those of the bonding pad. 11 . The method according to claim 8 , wherein at the step of disposing a bonding pad and a protection dam on a side of the pad, the conductive materials configuring the bonding pad and the first protection dam are simultaneously formed through evaporation.
Assignees
Inventors
Classifications
Treating the bonding area before connecting, e.g. by applying flux or cleaning · CPC title
Bond pads, in general · CPC title
Die-attach connectors · CPC title
Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title
by a substrate and the encapsulations · CPC title
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Frequently asked questions
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- What does patent US2018358305A1 cover?
- A wafer level package includes: a substrate having a circuit pattern unit, a pad spaced apart from the circuit pattern unit, a bonding pad disposed on a side of the pad, and a first protection dam; and a printed circuit board having a connection pad and a second protection dam, where the substrate and the printed circuit board are attached through the bonding and connection pads and the first a…
- Who is the assignee on this patent?
- Wisol Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W42/121. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Dec 13 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).