Ring network sysem using peripheral component interconnect express and setting method thereof

Patent metadata

Field	Value
Publication number	US-2018341607-A1
Application number	US-201816053605-A
Country	US
Kind code	A1
Filing date	Aug 2, 2018
Priority date	Dec 22, 2016
Publication date	Nov 29, 2018
Grant date	—

Abstract

A ring network system using peripheral component interconnect express (PCIe) is disclosed. The ring network system includes N PCIe bridges. Each of the N PCIe bridges is connected to an individual server and includes a first port and a second port. The second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges. Each of the N PCIe bridges includes an address mapping chip. The address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges.

First claim

What is claimed is:

1 . A ring network system using peripheral component interconnect express (PCIe), comprising:
N PCIe bridges, each of which is connected to an individual server and comprises a first port and a second port, wherein the second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges, N is a positive integer greater than or equal to 3, and i is a positive integer less than or equal to N, and wherein each of the N PCIe bridges comprises an address mapping chip, the address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges; wherein the address mapping chip of each of the N PCIe bridges sets a first address table and a second address table, and each of the N PCIe bridges further comprises:
a plurality of base address registers, each of which is configured to deliver a base address packet of one of the N PCIe bridges according to the first address table or the second address table; and
a plurality of translation registers set to configurably edit a destination address of the base address packet according to the mapping relationship for forwarding the base address packet;
wherein the first address table of the ith PCIe bridge is set to configurably map to a system address of an (((i−2+N) mod N)+1)th server connected to the ith PCIe bridge.

2 . A ring network system using peripheral component interconnect express (PCIe), comprising:
N PCIe bridges, each of which is connected to an individual server and comprises a first port and a second port, wherein the second port of an ith PCIe bridge of the N PCIe bridges is connected to the first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges, N is a positive integer greater than or equal to 3, and i is a positive integer less than or equal to N, and wherein each of the N PCIe bridges comprises an address mapping chip, the address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges; wherein the address mapping chip of each of the N PCIe bridges sets a first address table and a second address table, and each of the N PCIe bridges further comprises:
a plurality of base address registers, each of which is configured to deliver a base address packet of one of the N PCIe bridges according to the first address table or the second address table; and
a plurality of translation registers set to configurably edit a destination address of the base address packet according to the mapping relationship for forwarding the base address packet;
wherein the second address table of the ith PCIe bridge is set to configurably map to a system address of an ((i mod N)+1)th server connected to the ith PCIe bridge.

3 . The ring network system according to claim 2 , wherein the second address table of the ith PCIe bridge is set to configurably map to an address of each of at least portion of PCIe bridges of the second address table of the ((i mod N)+1)th PCIe bridge.

4 . The ring network system according to claim 1 , wherein the first address table of the ith PCIe bridge is set to configurably map to an address of each of at least portion of PCIe bridges of the first address table of the (((i−2+N) mod N)+1)th PCIe bridge.

5 . The ring network system according to claim 4 , wherein the second address table of the ith PCIe bridge is set to configurably map to a system address of an ((i mod N)+1)th server connected to the ith PCIe bridge, and the second address table of the ith PCIe bridge is set to configurably map to an address of each of at least portion of PCIe bridges of the second address table of the ((i mod N)+1)th PCIe bridge.

6 . The ring network system according to one of claim 1 , wherein when a disconnection between two of the PCIe bridges is detected, one of the two of the PCIe bridges disconnected is reset to be a numbered one bridge of the N PCIe bridges by resetting the first address table, the second address table and the mapping relationship of the ith PCIe bridge.

7 . A method for setting a ring network system using peripheral component interconnect express (PCIe), comprising:
connecting N PCIe bridges so that a second port of an ith PCIe bridge of the N PCIe bridges is connected to a first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges, wherein N is a positive integer greater than or equal to 3, i is a positive integer less than or equal to N, and each of the N PCIe bridges is connected to an individual server; and setting an address mapping chip of each of the N PCIe bridges so that the address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges; wherein each of the N PCIe bridges comprises a plurality of base address registers and a plurality of translation registers, wherein setting the address mapping chip of each of the N PCIe bridges comprises:
setting a first address table and a second address table of the address mapping chip of each of the N PCIe bridges;
setting each of the plurality of base address registers to deliver a base address packet of one of the N PCIe bridges according to the first address table or the second address table; and
setting each of the plurality of translation registers to configurably edit a destination address of the base address packet according to the mapping relationship for forwarding the base address packet;
wherein the first address table of the ith PCIe bridge is set to configurably map to a system address of an (((i−2+N) mod N)+1)th server connected to the ith PCIe bridge.

8 . A method for setting a ring network system using peripheral component interconnect express (PCIe), comprising:
connecting N PCIe bridges so that a second port of an ith PCIe bridge of the N PCIe bridges is connected to a first port of an ((i mod N)+1)th PCIe bridge of the N PCIe bridges, wherein N is a positive integer greater than or equal to 3, i is a positive integer less than or equal to N, and each of the N PCIe bridges is connected to an individual server; and setting an address mapping chip of each of the N PCIe bridges so that the address mapping chip of each of the N PCIe bridges configurably maps to a system address of each of at least portion of N servers connected by the N PCIe bridges and configurably maps to an address of each of at least portion of the N PCIe bridges for setting up a mapping relationship between the N PCIe bridges; wherein each of the N PCIe bridges comprises a plurality of base address registers and a plurality of translation registers, wherein setting the address mapping chip of each of the N PCIe bridges comprises:
setting a first address table and a second address table of the address mapping chip of each of the N PCIe bridges;
setting each of the plurality of base address registers to deliver a base address packet of one of the N PCIe bridges according to the first address table or the second address table; and
setting each of the plurality of translation registers to configurably edit a destination address of the base address packet according to the mapping relationship for forwa

Assignees

• Ind Tech Res Inst

Inventors

• Lee Chao-Tang
• Hsu Peng-Kai

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/404 Primary

  with address mapping · CPC title