Stacked independently contacted field effect transistor having electrically separated first and second gates
US-10164121-B2 · Dec 25, 2018 · US
Stacked nanowire semiconductor device
US2018337232A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018337232-A1 |
| Application number | US-201816050527-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 31, 2018 |
| Priority date | Jan 5, 2016 |
| Publication date | Nov 22, 2018 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method of forming a semiconductor device, the method comprising: forming a stack of nanowires, the stack comprising a first nanowire and a second nanowire; and forming first source and drain (S/D) regions of the first nanowire and second S/D regions of the second nanowire such that the first S/D regions comprise a different material than the second S/D regions. 2 . The method of claim 1 , wherein the first and second nanowires have different lengths. 3 . The method of claim 1 , wherein the stack comprises a third nanowire. 4 . The method of claim 3 , wherein the first, second, and third nanowires have different lengths. 5 . The method of claim 1 , further comprising forming a gate stack over channel regions of the first and second nanowires. 6 . The method of claim 5 , wherein the gate stack comprises one or more high-k dielectric materials. 7 . The method of claim 6 , wherein the gate stack comprises one or more workfunction metals. 8 . The method of claim 7 , wherein the gate stack comprises one or more metal gate conductor materials. 9 . The method of claim 1 , wherein the first and second nanowires comprise semiconductor material. 10 . The method of claim 1 , wherein the first and second nanowires comprise silicon. 11 . The method of claim 1 , wherein the stack is formed over a substrate. 12 . The method of claim 1 , wherein the first and second nanowires are patterned to different lengths. 13 . The method of claim 12 , wherein the stack comprises a third nanowire patterned to a different length than the first and second nanowires. 14 . The method of claim 1 , wherein the first S/D regions contact the first nanowire and the second S/D regions contact the second nanowire. 15 . The method of claim 1 , wherein the first S/D regions comprise dopants. 16 . The method of claim 1 , wherein the first S/D regions comprise an n-type dopant. 17 . The method of claim 1 , wherein the first S/D regions comprise a p-type dopant. 18 . The method of claim 1 , wherein the second S/D regions comprise dopants. 19 . The method of claim 1 , wherein the second S/D regions comprise an n-type dopant. 20 . The method of claim 1 , wherein the second S/D regions comprise a p-type dopant.
Assignees
Inventors
Classifications
Silicon, silicon germanium or germanium · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L29/0673Primary
Electricity · mapped topic
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- What does patent US2018337232A1 cover?
- A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L29/0673. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 22 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).