Logic devices, digital filters and video codecs including logic devices, and methods of controlling logic devices

Patent metadata

Field	Value
Publication number	US-2018332297-A1
Application number	US-201816043851-A
Country	US
Kind code	A1
Filing date	Jul 24, 2018
Priority date	Nov 19, 2012
Publication date	Nov 15, 2018
Grant date	—

Abstract

A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

First claim

1 - 20 . (canceled)

21 . A logic device comprising:
a configuration circuit including at least a first nonvolatile storage device, the configuration circuit being configured to store, in the first nonvolatile storage device, first configuration data, the configuration circuit being further configured to configure the logic device to perform a first operation associated with a first operation mode from among a plurality of operation modes based on the first configuration data stored in the first nonvolatile storage device.

22 . The logic device of claim 21 , further comprising:
a controller configured to control the configuration circuit to configure the logic device to perform the first operation.

23 . The logic device of claim 21 , further comprising:
a function circuit configured to perform the first operation associated with the first operation mode.

24 . The logic device of claim 23 , wherein the configuration circuit is configured to configure the function circuit to perform the first operation based on the first configuration data stored in the first nonvolatile storage device.

25 . The logic device of claim 21 , wherein the configuration circuit includes a second nonvolatile storage device, and wherein the configuration circuit is further configured to store, in the second nonvolatile storage device, second configuration data corresponding to a second operation mode from among the plurality of operation modes.

26 . The logic device of claim 25 , wherein the configuration circuit is configured to configure the logic device to perform a second operation associated with the second operation mode based on the second configuration data.

27 . The logic device of claim 26 , wherein the configuration circuit is configured to read the second configuration data from a first nonvolatile memory and store the second configuration data in the second nonvolatile storage device while the logic device performs the first operation.

28 . The logic device of claim 26 , wherein the configuration circuit is configured to read the second configuration data from a first nonvolatile memory and store the second configuration data in the second nonvolatile storage device while the logic device is being configured to perform the first operation.

29 . The logic device of claim 23 , wherein the configuration circuit includes a latch configured to output, to the function circuit, the first configuration data stored in the first nonvolatile storage device.

30 . The logic device of claim 29 , wherein the latch having an overlay configuration, the latch including
the first nonvolatile storage device and a second nonvolatile storage device, first and second transistors separately coupling the first nonvolatile storage device to first and second data lines, respectively, the first and second transistors configured to be controlled by a common first switching signal, third and fourth transistors separately coupling the second nonvolatile storage device to the first and second data lines, respectively, the third and fourth transistors configured to be controlled by a common second switching signal, fifth and sixth transistors connected to respective ends of the first nonvolatile storage device, the fifth and sixth transistors configured to be controlled by a common first control signal associated with activation or deactivation of the first nonvolatile storage device, and seventh and eighth transistors connected to respective ends of the second nonvolatile storage device, the seventh and eighth transistors configured to be controlled by a common second control signal associated with activation or deactivation of the second nonvolatile storage device.

31 . The logic device of claim 29 , wherein the latch having a multi configuration, the latch including
a plurality of nonvolatile storage devices including the first nonvolatile storage device, a plurality of transistors connected to an end of each of the plurality of nonvolatile storage devices, the plurality of transistors configured to be controlled by respective control signals associated with activation or deactivation of each of the plurality of the nonvolatile storage devices, and an output terminal configured to output data read from an activated nonvolatile storage device among the plurality of the nonvolatile storage devices to the function circuit.

32 . A digital filter comprising:
the logic device of claim 21 ; wherein the plurality of operation modes are associated with a filter function.

33 . The digital filter of claim 32 , further comprising:
a plurality of shifters, at least one of the plurality of shifters including a separate logic device that is configurable to shift a data word by a first bit number corresponding to each operation mode of the plurality of operation modes.

34 . A format conversion filter configured to convert a format of input data using the digital filter of claim 32 .

35 . A video codec for performing an encoding operation, the video codec comprising:
an intra predictor configured to perform a prediction operation using a digital filter that is configurable to perform a plurality of arithmetic operations associated with an intra prediction mode; wherein the digital filter is configurable to perform the plurality of arithmetic operations using a plurality of logic devices; wherein each of the logic devices includes, a configuration circuit including at least a first nonvolatile storage device, the configuration circuit being configured to store, in the first nonvolatile storage device, first configuration data, the configuration circuit being further configured to configure the logic device to perform a first operation from among the plurality of arithmetic operations based on the first configuration data stored in the first nonvolatile storage device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ho-Jung
• Chung U-In
• Choi Hyun-Sik

Classifications

• H03K19/17748

  Structural details of configuration resources · CPC title

• G11C11/41 Primary

  forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• H03K19/17772

  for powering on or off · CPC title

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title