Epitaxial growth of defect-free, wafer-scale single-layer graphene on thin films of cobalt

Patent metadata

Field	Value
Publication number	US-2018315599-A1
Application number	US-201615764370-A
Country	US
Kind code	A1
Filing date	Sep 28, 2016
Priority date	Oct 1, 2015
Publication date	Nov 1, 2018
Grant date	—

Abstract

A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.

First claim

1 . A method of forming a multilayer structure, the method comprising:
epitaxially depositing a graphene layer on a layer comprising cobalt, wherein the layer comprising cobalt is in contact with a dielectric layer, and further wherein the dielectric layer is in contact with a front wafer surface of a semiconductor wafer.

2 . The method of claim 1 wherein the semiconductor wafer comprises the front wafer surface, a back wafer surface, and a circumferential wafer edge joining the front wafer surface and the back wafer surface.

3 . The method of claim 2 wherein the semiconductor wafer comprises a material selected from the group consisting of silicon, silicon carbide, sapphire, aluminum nitride, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof.

4 . The method of claim 2 wherein the semiconductor wafer comprises a silicon wafer.

5 . The method of claim 1 wherein the semiconductor wafer comprises a dopant selected from the group consisting of boron (p type), gallium (p type), phosphorus (n type), antimony (n type), and arsenic (n type), and any combination thereof.

6 . The method of claim 1 wherein the dielectric layer comprises one or more of a silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer, or a multilayer comprising a silicon dioxide layer and a silicon nitride layer.

7 . The method of claim 1 wherein the layer comprising cobalt comprises a front cobalt layer surface, a back cobalt layer surface, and a bulk cobalt layer region between the front cobalt layer surface and the back cobalt layer surface, wherein the back cobalt layer surface is in contact with the dielectric layer.

8 . The method of claim 7 wherein the layer comprising cobalt is formed by depositing cobalt on the dielectric layer in contact with the front wafer surface of the semiconductor wafer.

9 . The method of claim 7 wherein the layer comprising cobalt is deposited by a technique selected from the group consisting of sputtering, evaporation, electrolytic plating, and metal foil bonding.

10 . The method of claim 7 wherein the layer comprising cobalt is between about 50 nanometers and about 20 micrometers thick.

11 . The method of claim 7 wherein the layer comprising cobalt is between about 50 nanometers and about 10 micrometers thick.

12 . The method of claim 7 wherein the layer comprising cobalt is between about 50 nanometers and about 1 micrometer thick.

13 . The method of claim 1 further comprising annealing a structure comprising the semiconductor wafer, the dielectric layer, and the layer comprising cobalt in a reducing atmosphere prior to epitaxially depositing the graphene layer on the layer comprising cobalt.

14 . The method of claim 1 wherein the layer comprising graphene is epitaxially deposited on the layer comprising cobalt according to the following steps:
contacting the front cobalt layer surface of the layer comprising cobalt with a carbon-containing gas in a reducing atmosphere at a temperature sufficient to nucleate carbon atoms on the front cobalt layer surface; and
precipitating carbon atoms to thereby epitaxially deposit the layer of graphene on the front cobalt layer surface.

15 . The method of claim 14 wherein the carbon atoms are precipitated by cooling the layer comprising cobalt in contact with a dielectric layer.

16 . The method of claim 14 wherein the carbon-containing gas is selected from the group consisting of methane, ethane, ethylene, acetylene, propane, propylene, propyne, butanes, butylenes, butynes, and combinations thereof.

17 . The method of claim 14 wherein the reducing atmosphere comprises hydrogen gas.

18 . The method of claim 14 further comprising annealing a structure comprising the semiconductor wafer, the dielectric layer, and the layer comprising cobalt in a reducing atmosphere prior to contacting the layer surface of the layer comprising cobalt with a carbon-containing gas.

19 . The method of claim 1 wherein the graphene layer has a single mono-atomic thickness.

20 . The method of claim 1 wherein the graphene layer has a quality factor of at least about 4.

21 . The method of claim 1 wherein the graphene layer has a quality factor of at least about 7, or at least about 7.5.

22 . A multilayer structure comprising:
a semiconductor wafer, the semiconductor wafer comprising a front wafer surface, a back wafer surface, and a circumferential wafer edge joining the front wafer surface and the back wafer surface; a dielectric layer in contact with the front wafer surface of the semiconductor wafer; a layer comprising cobalt in contact with the dielectric layer, the layer comprising cobalt comprising a front cobalt layer surface, a back cobalt layer surface, and a bulk cobalt layer region between the front cobalt layer surface and the back cobalt layer surface, wherein the back layer cobalt surface is in contact with the dielectric layer; and a graphene layer in contact with the front cobalt layer surface of the layer comprising cobalt.

23 . The multilayer structure of claim 22 wherein the semiconductor wafer comprises a material selected from the group consisting of silicon, silicon carbide, sapphire, aluminum nitride, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof.

24 . The multilayer structure of claim 22 wherein the semiconductor wafer comprises a silicon wafer.

25 . The multilayer structure of claim 22 wherein the semiconductor wafer comprises a dopant selected from the group consisting of boron (p type), gallium (p type), phosphorus (n type), antimony (n type), and arsenic (n type), and any combination thereof.

26 . The multilayer structure of claim 22 wherein the dielectric layer comprises one or more of a silicon dioxide layer, a silicon nitride layer, a silicon oxynitride layer, or a multilayer comprising a silicon dioxide layer and a silicon nitride layer.

27 . The multilayer structure of claim 22 wherein the dielectric layer is between about 10 nanometers and about 1000 nanometers thick.

28 . The multilayer structure of claim 22 wherein the dielectric layer is between about 50 nanometers and about 300 nanometers thick.

29 . The multilayer structure of claim 22 wherein the layer comprising cobalt is between about 50 nanometers and about 20 micrometers thick.

30 . The multilayer structure of claim 22 wherein the layer comprising cobalt is between about 50 nanometers and about 10 micrometers thick.

31 . The multilayer structure of claim 22 wherein the layer comprising cobalt is between about 50 nanometers and about 1 micrometer thick.

32 . The multilayer structure of claim 22 wherein the graphene layer has a single mono-atomic thickness.

33 . The multilayer structure of claim 22 through 32 wherein the graphene layer has a quality factor of at least about 4.

34 . The multilayer structure of claim 22 wherein the graphene layer has a quality factor of at least about 7, or at least about 7.5.

Assignees

• Sunedison Semiconductor Ltd
• Univ Illinois

Inventors

• Berry Vikas
• Behura Sanjay
• Nguyen Phong
• Seacrist Michael R

Classifications

• H10P14/3248

  consisting of two layers · CPC title

• H10P14/3241

  being conductive materials · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/2911

  Arsenides · CPC title