Low dielectric constant oxide and low resistance op stack for 3d nand application

Patent metadata

Field	Value
Publication number	US-2018315592-A1
Application number	US-201815958747-A
Country	US
Kind code	A1
Filing date	Apr 20, 2018
Priority date	Apr 27, 2017
Publication date	Nov 1, 2018
Grant date	—

Abstract

Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH 4 ) is introduced to a PECVD process to form Si x Ge (1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.

First claim

What is claimed is:

1 . A method of manufacturing a memory device stack, comprising:
positioning a substrate in a PECVD chamber; introducing octamethylcyclotetrasiloxane precursor to the PECVD chamber to deposit a silicon oxide layer over the substrate; and depositing a polysilicon layer over the silicon oxide layer.

2 . The method of claim 1 , wherein the depositing the polysilicon layer over the silicon oxide layer comprises:
introducing silane and germane to the PECVD chamber to deposit the polysilicon layer.

3 . The method of claim 1 , wherein the introducing octamethylcyclotetrasiloxane precursor to the PECVD chamber to deposit the silicon oxide layer over the substrate occurs at a plasma density of about 27 megahertz.

4 . The method of claim 1 , further comprising:
bombarding the silicon oxide layer with an RF frequency of between about 300 kHz and about 400 kHz.

5 . The method of claim 1 , further comprising:
plasma treating an interface between the silicon oxide layer and the polysilicon layer, wherein the plasma treating comprises introducing NH 3 /N 2 to the PECVD chamber.

6 . The method of claim 1 , wherein depositing the polysilicon layer over the silicon oxide layer comprises:
introducing one or more precursors selected from the group consisting of silane, argon, and helium, and one or more dopant precursors selected from the group consisting of phosphine and diborane, to the PECVD chamber to deposit an amorphous silicon layer over the silicon oxide layer; and annealing the amorphous silicon layer to form the polysilicon layer.

7 . The method of claim 1 , wherein depositing the polysilicon layer over the silicon oxide layer comprises:
introducing at least one silicon precursor selected from the group consisting of silane and germane to the PECVD chamber to form a Si x Ge (1-x) film.

8 . A method of manufacturing a memory device stack, comprising:
positioning a substrate in a PECVD chamber; depositing a silicon oxide layer over the substrate; and introducing a silicon precursor and germane to the PECVD chamber to form a Si x Ge (1-x) film over the silicon oxide layer.

9 . The method of claim 8 , wherein the depositing a silicon oxide layer over the substrate comprises:
introducing OMCTS precursor to the PECVD chamber to deposit the silicon oxide layer.

10 . The method of claim 8 , further comprising:
annealing the Si x Ge (1-x) film to form a polysilicon layer over the silicon oxide layer.

11 . The method of claim 8 , further comprising:
generating a plasma in the PECVD chamber.

12 . The method of claim 11 , wherein introducing the silicon precursor and germane to the PECVD chamber occurs before generating the plasma in the PECVD chamber.

13 . The method of claim 8 , further comprising:
plasma treating an interface between the silicon oxide layer and the polysilicon layer, wherein the plasma treatment comprises introducing NH 3 /N 2 to the PECVD chamber.

14 . The method of claim 8 , wherein the Si x Ge (1-x) film is doped.

15 . The method of claim 14 , where in the Si x Ge (1-x) film is doped with phosphine.

16 . A memory device, comprising:
a substrate; a silicon oxide layer disposed over the substrate, the silicon oxide layer having a dielectric constant between about 2.5 and about 3.2; and a polysilicon layer disposed over the silicon oxide layer.

17 . The memory device of claim 16 , wherein the dielectric constant of the silicon oxide layer is between about 2.8 and about 3.0.

18 . The memory device of claim 16 , wherein the silicon oxide layer is deposited on and in contact with the substrate and wherein the polysilicon layer is deposited on and in contact with the silicon oxide layer.

19 . The memory device of claim 16 , wherein the polysilicon layer is an n-type polysilicon layer, and wherein the n-type polysilicon layer has a resistivity of less than about 0.5×10 −3 ohm*cm.

20 . The memory device of claim 16 , wherein the polysilicon layer is a p-type polysilicon layer, and wherein the p-type polysilicon layer has a resistivity of less than about 1.5×10 −3 ohm*cm.

Assignees

• Applied Materials Inc

Inventors

• Han Xinhai
• Yim Kang Sub
• Jiang Zhijun
• Padhi Deenesh

Classifications

• H10P14/3454

  Amorphous · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6684

  the compound comprising silicon and oxygen · CPC title

• H10P14/6532

  by exposure to a plasma · CPC title

• H10P14/6524

  the substance being nitrogen · CPC title