Storage management for machine learning at autonomous machines

Patent metadata

Field	Value
Publication number	US-2018314249-A1
Application number	US-201715581124-A
Country	US
Kind code	A1
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Nov 1, 2018
Grant date	—

Abstract

A mechanism is described for facilitating storage management for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting one or more components associated with machine learning, where the one or more components include memory and a processor coupled to the memory, and where the processor includes a graphics processor. The method may further include allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, where the storage and hardware portions are precise for implementation and processing of the training set.

First claim

What is claimed is:

1 . An apparatus comprising:
detection/observation logic, as facilitated by or at least partially incorporated into a processor, to detect one or more components associated with machine learning, wherein the one or more components include memory and the processor coupled to the memory, wherein the processor includes a graphics processor; and adaptive training storage selection logic, as facilitated by or at least partially incorporated into the processor, to allocate a storage portion of the memory and a hardware portion of the processor to a machine learning training set, wherein the storage and hardware portions are precise for implementation and processing of the training set.

2 . The apparatus of claim 1 , wherein the adaptive training storage selection logic is further to analyze the one or more components to determine the storage portion and the hardware portion of the memory and the graphics processor, respectively, wherein the one or more components further include one or more of one or more compilers, one or more drivers, schedulers, compute clusters, compute elements, and caches.

3 . The apparatus of claim 1 , wherein a compiler the one or more compilers to detect the storage and hardware portions, and wherein a driver of the one or more drivers to configure the storage and hardware portions to allow for precision in the implementation and processing of the training set.

4 . The apparatus of claim 1 , further comprising unified memory logic, as facilitated by or at least partially incorporated into the processor, to generate a single unified memory system having the memory and the graphics processor, wherein single unified memory system further includes the caches coupled to the graphics processor and one or more other graphics processors to form a communication network for transmission of data between multiple graphics processors including the graphics processor and the one or more other graphics processors.

5 . The apparatus of claim 4 , further comprising cache coherency logic, as facilitated by or at least partially incorporated into the processor, to introduce cache coherency within the single unified memory system, wherein introducing the cache coherency includes providing a page level coherency across the multiple graphics processors and an ability to exchange ownership between the multiple graphics processors at one or more levels of the single unified memory system, wherein each of the one or more levels includes at least two graphics processors and at least two caches associated with the two graphics processors.

6 . The apparatus of claim 1 , further comprising high bandwidth memory logic, as facilitated by or at least partially incorporated into the processor, to form a high bandwidth memory (HBM) system employing the graphics processor coupled to one or more of the compute clusters further coupled with the memory through one or more of the compute elements, wherein the HBM system is facilitated through one or more HBM channels, wherein a scheduler to scheduler tasks or threads relating to the graphics processor based on the HBM system.

7 . The apparatus of claim 1 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

8 . A method comprising:
detecting one or more components associated with machine learning, wherein the one or more components include memory and a processor coupled to the memory, wherein the processor includes a graphics processor; and allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, wherein the storage and hardware portions are precise for implementation and processing of the training set.

9 . The method of claim 8 , further comprising analyzing the one or more components to determine the storage portion and the hardware portion of the memory and the graphics processor, respectively, wherein the one or more components further include one or more of one or more compilers, one or more drivers, schedulers, compute clusters, compute elements, and caches.

10 . The method of claim 8 , wherein a compiler the one or more compilers to detect the storage and hardware portions, and wherein a driver of the one or more drivers to configure the storage and hardware portions to allow for precision in the implementation and processing of the training set.

11 . The method of claim 8 , further comprising generating a single unified memory system having the memory and the graphics processor, wherein single unified memory system further includes the caches coupled to the graphics processor and one or more other graphics processors to form a communication network for transmission of data between multiple graphics processors including the graphics processor and the one or more other graphics processors.

12 . The method of claim 11 , further comprising introducing cache coherency within the single unified memory system, wherein introducing the cache coherency includes providing a page level coherency across the multiple graphics processors and an ability to exchange ownership between the multiple graphics processors at one or more levels of the single unified memory system, wherein each of the one or more levels includes at least two graphics processors and at least two caches associated with the two graphics processors.

13 . The method of claim 8 , further comprising forming a high bandwidth memory (HBM) system employing the graphics processor coupled to one or more of the compute clusters further coupled with the memory through one or more of the compute elements, wherein the HBM system is facilitated through one or more HBM channels, wherein a scheduler to scheduler tasks or threads relating to the graphics processor based on the HBM system.

14 . The method of claim 8 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

15 . At least one machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
detecting one or more components associated with machine learning, wherein the one or more components include memory and a processor coupled to the memory, wherein the processor includes a graphics processor; and allocating a storage portion of the memory and a hardware portion of the processor to a machine learning training set, wherein the storage and hardware portions are precise for implementation and processing of the training set.

16 . The machine-readable medium of claim 15 , wherein the operations further comprise analyzing the one or more components to determine the storage portion and the hardware portion of the memory and the graphics processor, respectively, wherein the one or more components further include one or more of one or more compilers, one or more drivers, schedulers, compute clusters, compute elements, and caches.

17 . The machine-readable medium of claim 15 , wherein a compiler the one or more compilers to detect the storage and hardware portions, and wherein a driver of the one or more drivers to configure the storage and hardware portions to allow for precision in the implementation and processing of the training set.

18 . The machine-readable medium of claim 15 , wherein the operations further comprise generating a single unified memory system having the memory and the graphics processor, wherein single unified memory system further includes the caches coupled to the graphics processor and one or more other

Assignees

• Intel Corp

Inventors

• Appu Abhishek R
• Weast John C
• Baghsorkhi Sara S
• Gottschlich Justin E
• Surti Prasoonkumar
• Sakthivel Chandrasekaran
• Koker Altug
• Akhbari Farshad
• Chen Feng
• Kim Dukhwan
• Srinivasa Narayan
• Satish Nadathur Rajagopalan
• Sinha Kamal
• Ray Joydeep
• Vembu Balaji
• Macpherson Mike B
• Hurd Linda L
• Jahagirdar Sanjeev
• Ranganathan Vasanth

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/08

  Learning methods · CPC title

• G06N3/063

  using electronic means · CPC title