Adaptive modulation scheme of mosfet driver key parameters for improved voltage regulator efficiency and system reliability

Patent metadata

Field	Value
Publication number	US-2018309366-A1
Application number	US-201715491561-A
Country	US
Kind code	A1
Filing date	Apr 19, 2017
Priority date	Apr 19, 2017
Publication date	Oct 25, 2018
Grant date	—

Abstract

Systems and methods for adaptive modulation of MOSFET driver key parameters for improved voltage regulator efficiency and reliability in a voltage regulator may include a power stage. The power stage may include a high side switch including a high side gate, a peak voltage detection circuit, and a high side driver strength modulator circuit. The high side driver strength modulator circuit may determine a high side driver strength level. The high side driver strength modulator circuit may also connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level. The high side driver strength modulator circuit may also disconnect a remaining subset of the set of high side gate drivers from the high side gate.

First claim

What is claimed is:

1 . A voltage regulator, comprising:
a power stage including: a high side switch including a high side gate; a peak voltage detection circuit coupled to the high side switch to provide a voltage stress level based on a high side output voltage of the high side switch; and a high side driver strength modulator circuit coupled to the peak voltage detection circuit configured to: determine a high side driver strength level for a set of high side gate drivers based on one or more of a load current level of the power stage and the voltage stress level; connect a subset of the set of high side gate drivers to the high side gate based on the high side driver strength level; and disconnect a remaining subset of the set of high side gate drivers from the high side gate.

2 . The voltage regulator of claim 1 , the power stage further comprising:
a low side switch including a low side gate; and a low side driver strength modulator circuit coupled to the peak voltage detection circuit configured to: determine a low side driver strength level for a set of low side gate drivers based on one or more of the load current level of the power stage and the voltage stress level; connect a subset of the set of low side gate drivers to the low side gate based on the low side driver strength level; and disconnect a remaining subset of the set of low side gate drivers from the low side gate.

3 . The voltage regulator of claim 2 , the high side driver strength modulator circuit further comprising:
a source impedance modulator circuit; a set of high side driver switches, each coupled between a corresponding high side gate driver of the set of high side gate drivers and the high side gate, wherein the connection of the subset of the set of high side gate drivers to the high side gate further comprises: the source impedance modulator circuit configured to close a subset of the set of high side driver switches to connect the subset of the set of high side gate drivers to the high side gate; a sink impedance modulator circuit; and a set of low side driver switches, each coupled between a corresponding low side gate driver of the set of low side gate drivers and the low side gate, wherein the connection of the subset of the set of low side gate drivers to the low side gate further comprises: the sink impedance modulator circuit configured to close a subset of the set of low side driver switches to connect the subset of the set of low side gate drivers to the low side gate.

4 . The voltage regulator of claim 1 , the power stage further comprising:
a driver voltage optimizer circuit configured to adjust a driver voltage level for the set of high side gate drivers and the set of low side gate drivers based on the load current level of the power stage.

5 . The voltage regulator of claim 4 , wherein the driver voltage optimizer circuit to adjust the driver voltage level further comprises the driver voltage optimizer circuit configured to:
reduce the driver voltage level when the driver voltage optimizer circuit determines that the load current level is less than or equal to a light load current threshold level; and increase the driver voltage level when the driver voltage optimizer circuit determines that the load current level is greater than a heavy load condition threshold level.

6 . The voltage regulator of claim 1 , wherein
higher positive load current levels correlate to higher driver voltage levels and lower positive load current levels correlate to lower driver voltage levels, and wherein higher magnitude negative load current levels correlate to higher driver voltage levels and lower magnitude negative load current levels correlate to lower driver voltage values.

7 . The voltage regulator of claim 1 , the power stage further comprising:
a dead-time management circuit configured to: when the dead-time management circuit determines that a current temperature of the power stage is less than or equal to a low temperature region threshold, adjust a programmable portion of a dead-time duration for the set of high side gate drivers and the set of low side gate drivers to a low temperature duration value.

8 . The voltage regulator of claim 7 , the dead-time management circuit further configured to:
when the dead-time management circuit determines that the current temperature of the power stage is greater than or equal to a high temperature region threshold, adjust the programmable portion of the dead-time duration for the set of high side gate drivers and the set of low side gate drivers to a high temperature duration value.

9 . The voltage regulator of claim 8 , wherein the dead-time duration includes the programmable portion of the dead-time duration and a dynamic portion of the dead-time duration proportional to a change in temperature of the power stage when the power stage is in an operating temperature region.

10 . The voltage regulator of claim 2 , wherein each of the high side switch and the low side switch is a metal-oxide-semiconductor-field-effect-transistors (MOSFETs).

11 . A method comprising:
providing, by a peak voltage detection circuit of a power stage of a voltage regulator, a voltage stress level based on a high side output voltage of a high side switch of the power stage; determining, by a high side driver strength modulator circuit of the power stage, a high side driver strength level for a set of high side gate drivers of the power stage based on one or more of a load current level of the power stage and the voltage stress level; connecting a subset of the set of high side gate drivers to a high side gate of the high side switch based on the high side driver strength level; and disconnecting a remaining subset of the set of high side gate drivers from the high side gate.

12 . The method of claim 11 , further comprising:
determining, by a low side driver strength modulator circuit of the power stage, a low side driver strength level for a set of low side gate drivers of the power stage based on one or more of the load current level of the power stage and the voltage stress level; connecting a subset of the set of low side gate drivers to a low side gate of a low side switch based on the low side driver strength level; and disconnecting a remaining subset of the set of low side gate drivers from the low side gate.

13 . The method of claim 12 , wherein connecting the subset of the set of high side gate drivers to the high side gate further comprises:
closing, by a source impedance modulator circuit, a subset of a set of high side driver switches of the power stage to connect the subset of the set of high side gate drivers to the high side gate; and wherein connecting the subset of the set of low side gate drivers to the low side gate further comprises: closing, by a sink impedance modulator circuit, a subset of a set of low side driver switches to connect the subset of the set of low side gate drivers to the low side gate.

14 . The method of claim 11 , further comprising:
adjusting, by a driver voltage optimizer circuit, a driver voltage level for the set of high side gate drivers and the set of low side gate drivers based on the load current level of the power stage.

15 . The method of claim 14 , wherein adjusting the driver voltage level further comprising:
reducing the driver voltage level when the driver voltage optimizer circuit determines that the load current level is less than or equal to a light load current threshold level; and increasing the driver voltage level when the driver voltage optimizer circuit determines tha

Assignees

• Dell Products Lp

Inventors

• Zhang Kejiu
• Luo Shiguo
• Johnson Ralph H

Classifications

• H03K17/082 Primary

  by feedback from the output to the control circuit · CPC title

• H03K17/166

  Soft switching · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title