Method for fabricating microelectronic package with surface mounted passive element

Patent metadata

Field	Value
Publication number	US-2018294255-A1
Application number	US-201815886813-A
Country	US
Kind code	A1
Filing date	Feb 1, 2018
Priority date	Apr 11, 2017
Publication date	Oct 11, 2018
Grant date	—

Abstract

A method for fabricating a microelectronic package is disclosed. A packaged substrate having a chip surrounded by a molding compound is prepared. An RDL structure is formed on the chip. Bump pads and SMD pads are disposed in a topmost level of metal interconnect of the RDL structure. A passivation layer covers the RDL structure. The passivation layer is subjected to a lithographic process to form bump pad openings and an SMD opening in the passivation layer. The bump pads are exposed, respectively, through the bump pad openings. The SMD pads are exposed through the SMD opening. Bumps are formed on the bump pads through the bump pad openings, respectively. A passive element is mounted on the SMD pads.

First claim

What is claimed is:

1 . A method for fabricating a microelectronic package, comprising:
providing a packaged substrate having thereon at least one chip surrounded by a molding compound; forming a re-distribution layer (RDL) structure on the chip, the RDL structure comprising n levels of metal interconnect, wherein n is an integer that is greater than or equal to 2, wherein bump pads and surface mount device (SMD) pads are disposed in a topmost level of the n levels of metal interconnect of the RDL structure; forming a passivation layer covering the RDL structure; subjecting the passivation layer to a lithographic process to form bump pad openings and an SMD opening in the passivation layer, wherein the bump pads are exposed, respectively, through the bump pad openings, and the SMD pads are exposed through the SMD opening; forming bumps on the bump pads through the bump pad openings, respectively; and mounting a passive element on the SMD pads.

2 . The method for fabricating a microelectronic package according to claim 1 , wherein the passivation layer comprises a polyimide layer.

3 . The method for fabricating a microelectronic package according to claim 1 , wherein the bumps comprises C4 bumps.

4 . The method for fabricating a microelectronic package according to claim 1 , wherein each of the bumps comprises a metal stud and a solder layer on the metal stud.

5 . The method for fabricating a microelectronic package according to claim 1 , wherein before mounting the passive element on the SMD pads, the method further comprises:
performing a pre-cleaning process to remove unwanted substance from an exposed top surfaces of the SMD pads.

6 . The method for fabricating a microelectronic package according to claim 1 , wherein the passive element comprises a decoupling capacitor, a resistor, an inductor, or an integrated passive device (IPD).

7 . The method for fabricating a microelectronic package according to claim 1 , wherein the passive element has a thickness t ranging between 20-30 micrometers.

8 . The method for fabricating a microelectronic package according to claim 1 , wherein a top surface of the passive element is lower than a top surface of each of the bumps.

9 . The method for fabricating a microelectronic package according to claim 1 , wherein the packaged substrate comprises a fan-out wafer-level-package (Fan-Out WLP).

10 . A method for fabricating a microelectronic package, comprising:
providing a packaged substrate having thereon at least one chip surrounded by a molding compound; forming a re-distribution layer (RDL) structure on the chip, the RDL structure comprising n levels of metal interconnect, wherein n is an integer that is greater than or equal to 2, wherein bump pad and surface mount device (SMD) pads are disposed in a topmost level of the n levels of metal interconnect of the RDL structure; forming a passivation layer covering the RDL structure; subjecting the passivation layer to a lithographic process to form bump pad openings in the passivation layer, wherein the bump pads are exposed, respectively, through the bump pad openings; forming under-bump metallization (UBM) pads and SMD pads on the passivation layer; forming solder balls or bumps on the UBM pads, respectively; and mounting a passive element on the SMD pads.

11 . The method for fabricating a microelectronic package according to claim 10 , wherein said forming UBM pads and SMD pads on the passivation layer comprises:
forming a mask layer on the passivation layer; subjecting the mask layer to a lithographic process to form openings in the mask layer; and performing a plating process to form the UBM pads and SMD pads in the openings, respectively.

12 . The method for fabricating a microelectronic package according to claim 11 , wherein after forming the UBM pads and the SMD pads on the passivation layer, the mask layer is removed.

13 . The method for fabricating a microelectronic package according to claim 11 , wherein the mask layer is a photoresist layer.

14 . The method for fabricating a microelectronic package according to claim 10 , wherein the passive element comprises a decoupling capacitor, a resistor, an inductor, or an integrated passive device (IPD).

15 . The method for fabricating a microelectronic package according to claim 10 , wherein the packaged substrate comprises a fan-out wafer-level-package (Fan-Out WLP).

16 . A method for fabricating a microelectronic package, comprising:
providing a packaged substrate having thereon at least one chip surrounded by a molding compound; forming a re-distribution layer (RDL) structure on the chip, the RDL structure comprising n levels of metal interconnect in a dielectric layer, wherein n is an integer that is greater than or equal to 2, wherein bump pads are disposed in a topmost level of the n levels of metal interconnect of the RDL structure, and surface mount device (SMD) pads are disposed in a lowest level of the n levels of metal interconnect of the RDL structure; forming a passivation layer covering the RDL structure; subjecting the passivation layer to a lithographic process to form bump pad openings in the passivation layer and an SMD opening in the passivation layer and the dielectric layer, wherein the bump pads are exposed, respectively, through the bump pad openings, and the SMD pads are exposed through the SMD opening; forming bumps on the bump pads through the bump pad openings, respectively; and mounting a passive element on the SMD pads within the SMD opening.

17 . The method for fabricating a microelectronic package according to claim 16 , wherein the passivation layer comprises a polyimide layer.

18 . The method for fabricating a microelectronic package according to claim 16 , wherein the bumps comprises C4 bumps.

19 . The method for fabricating a microelectronic package according to claim 16 , wherein each of the bumps comprises a metal stud and a solder layer on the metal stud.

20 . The method for fabricating a microelectronic package according to claim 16 , wherein before mounting the passive element on the SMD pads, the method further comprises:
performing a pre-cleaning process to remove unwanted substance from an exposed top surfaces of the SMD pads.

21 . The method for fabricating a microelectronic package according to claim 16 , wherein the passive element comprises a decoupling capacitor, a resistor, an inductor, or an integrated passive device (IPD).

Assignees

• Mediatek Inc

Inventors

• Liu Hsing-Chih

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W70/655

  Fan-out layouts · CPC title