Semiconductor device having resistance elements and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2018277618-A1
Application number	US-201815992645-A
Country	US
Kind code	A1
Filing date	May 30, 2018
Priority date	Feb 19, 2016
Publication date	Sep 27, 2018
Grant date	—

Abstract

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration C X . The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration C Y lower than the concentration C X . A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration C X . A sign of a TCR of the second polycrystalline silicon changes at the concentration C Y .

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first polycrystalline silicon having a negative temperature coefficient and having a first width; and a second polycrystalline silicon having a positive temperature coefficient and having a second width larger than the first width.

2 . The semiconductor device according to claim 1 , wherein:
the first polycrystalline silicon contains first impurities at a first concentration; and the second polycrystalline silicon contains the first impurities at the first concentration.

3 . The semiconductor device according to claim 1 , wherein:
the first polycrystalline silicon contains first impurities at a first concentration; and the second polycrystalline silicon contains the first impurities at a second concentration lower than the first concentration.

4 . The semiconductor device according to claim 3 , wherein the first concentration and the second concentration are higher than or equal to 1×10 20 cm −3 and lower than or equal to 1×10 21 cm −3 .

5 . The semiconductor device according to claim 1 , wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected.

6 . The semiconductor device according to claim 1 , wherein the first impurities are p-type impurities.

7 . A semiconductor device fabrication method comprising:
acquiring a relationship between a concentration of first impurities and a temperature coefficient for a first polycrystalline silicon having a first width and a second polycrystalline silicon having a second width larger than the first width; setting, on the basis of the relationship, a first concentration of the first impurities in the first polycrystalline silicon and a second concentration of the first impurities in the second polycrystalline silicon; and forming the first polycrystalline silicon containing the first impurities at the first concentration and the second polycrystalline silicon containing the first impurities at the second concentration.

8 . The semiconductor device fabrication method according to claim 7 , wherein:
the second concentration is lower than the first concentration; a sign of the temperature coefficient of the first polycrystalline silicon changes at the first concentration; and a sign of the temperature coefficient of the second polycrystalline silicon changes at the second concentration.

9 . The semiconductor device fabrication method according to claim 7 , wherein:
the first polycrystalline silicon containing the first impurities at the first concentration has a negative temperature coefficient; and the second polycrystalline silicon containing the first impurities at the second concentration has a positive temperature coefficient.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Ema Taiji
• Misawa Nobuhiro
• Kumeno Kazuyuki
• Yasuda Makoto

Classifications

• H10D62/10 Primary

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H01L27/0629

  Electricity · mapped topic

• H01L27/0802

  Electricity · mapped topic