Method of manufacturing semiconductor element

US2018247871A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018247871-A1
Application numberUS-201815902756-A
CountryUS
Kind codeA1
Filing dateFeb 22, 2018
Priority dateFeb 27, 2017
Publication dateAug 30, 2018
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of manufacturing a semiconductor element includes: providing a wafer having a semiconductor layered body on a sapphire substrate; irradiating a laser light in an interior region of the sapphire substrate to create cracks in the sapphire substrate by performing a first scan to irradiate the laser light at a first depth with a first pulse energy to create a first modified region, and a second scan following the first scan to irradiate the laser light at a second depth with a second pulse energy greater than the first pulse energy along and within the first modified region; and dividing the wafer by extending the cracks to obtain a semiconductor element.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of manufacturing a semiconductor element comprising: providing a wafer having a semiconductor layered body on a sapphire substrate; irradiating a laser light in an interior region of the sapphire substrate to create cracks in the sapphire substrate by performing a first scan to irradiate the laser light at a first depth with a first pulse energy to create a first modified region, and a second scan following the first scan to irradiate the laser light at a second depth with a second pulse energy greater than the first pulse energy along and within the first modified region; and dividing the wafer by extending the cracks to obtain a semiconductor element. 2 . The method of manufacturing a semiconductor element according to claim 1 , wherein the second pulse energy with respect to the first pulse energy is in a range of 110% to 300%. 3 . The method of manufacturing a semiconductor element according to claim 1 , wherein the first scan and the second scan are carried out along a m-axis of sapphire used for the sapphire substrate. 4 . The method of manufacturing a semiconductor element according to claim 1 , wherein the first scan and the second scan are carried out along an a-axis of sapphire used for the sapphire substrate. 5 . The method of manufacturing a semiconductor element according to claim 4 , wherein the first scan is a first a-axis direction scan with a first spot interval, and the second scan is a second a-axis direction scan with a second spot interval that is smaller than the first spot interval. 6 . The method of manufacturing a semiconductor element according to claim 5 , wherein the second spot interval with respect to the first spot interval is in a range of 20% to 80%. 7 . The method of manufacturing a semiconductor element according to claim 5 , wherein the irradiating of the laser light further includes performing a first m-axis direction scan to irradiate the laser light at a third depth along a m-axis of the sapphire with a third spot interval and a third pulse energy to create a third modified region, and a second m-axis direction scan following the first m-axis direction scan to irradiate the laser light at a fourth depth along the m-axis within a third modified region with a fourth spot interval and a fourth pulse energy greater than the third pulse energy. 8 . The method of manufacturing a semiconductor element according to claim 7 , wherein the fourth spot interval is greater than the third spot interval. 9 . The method of manufacturing a semiconductor element according to claim 7 , wherein the third spot interval is smaller than the first spot interval. 10 . The method of manufacturing a semiconductor element according to claim 7 , wherein the first a-axis direction scan and the second a-axis direction scan are successively carried out such that the first a-axis direction scan is carried out from a first end to a second end of the wafer and the second a-axis direction scan is carried out from the second end to the first end of the wafer, and before or after the first a-axis direction scan and the second a-axis direction scan are carried out, the first m-axis direction scan and the second m-axis direction scan are successively carried out such that the first m-axis direction scan is carried out from the first end to the second end of the wafer and the second m-axis direction scan is carried out from the second end to the first end of the wafer. 11 . The method of manufacturing a semiconductor element according to claim 7 , wherein the second a-axis direction scan is performed within 10 seconds after the first a-axis direction scan, and the second m-axis direction scan is performed within 10 seconds after the first m-axis direction scan. 12 . The method of manufacturing a semiconductor element according to claim 7 , wherein scan speeds of the first a-axis direction scan, the second a-axis direction scan, the first m-axis direction scan, and the second m-axis direction scan are respectively set to allow a reciprocating scanning along a diameter of the wafer to complete within 10 seconds. 13 . The method of manufacturing a semiconductor element according to claim 7 , wherein the fourth spot interval with respect to the third spot interval is in a range of 110% to 300%. 14 . The method of manufacturing a semiconductor element according to claim 7 , wherein the forth pulse energy with respect to the third pulse energy is in a range of 110% to 300%. 15 . The method of manufacturing a semiconductor element according to claim 7 , wherein the second pulse energy is smaller than the fourth pulse energy, and the second spot interval is smaller than the fourth spot interval. 16 . The method of manufacturing a semiconductor element according to claim 7 , wherein the first pulse energy, the second pulse energy, the third pulse energy, and the fourth pulse energy are respectively within a range of 0.6 μJ to 10 μJ. 17 . The method of manufacturing a semiconductor element according to claim 7 , wherein a pulse width of the laser light respectively used in the first a-axis direction scan, the second a-axis direction scan, the first m-axis direction scan, and the second m-axis direction scan is in a range of 100 fsec to 10 psec.

Assignees

Inventors

Classifications

  • H10P54/00Primary

    Cutting or separating of wafers, substrates or parts of devices · CPC title

  • for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks · CPC title

  • being semiconducting · CPC title

  • Electricity · mapped topic

  • H01L21/78Primary

    Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2018247871A1 cover?
A method of manufacturing a semiconductor element includes: providing a wafer having a semiconductor layered body on a sapphire substrate; irradiating a laser light in an interior region of the sapphire substrate to create cracks in the sapphire substrate by performing a first scan to irradiate the laser light at a first depth with a first pulse energy to create a first modified region, and a s…
Who is the assignee on this patent?
Nichia Corp
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 30 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).