Integrating metal-insulator-metal capacitors with air gap process flow

Patent metadata

Field	Value
Publication number	US-2018233446-A1
Application number	US-201815951208-A
Country	US
Kind code	A1
Filing date	Apr 12, 2018
Priority date	Jul 25, 2016
Publication date	Aug 16, 2018
Grant date	—

Abstract

Semiconductor devices are provided which have MIM (metal-insulator-metal) capacitor structures that are integrated within air gaps of on-chip interconnect structures, as well as methods for integrating MIM capacitor formation as part of an air gap process flow for fabricating on-chip interconnect structures. For example, a semiconductor device includes a dielectric layer with a first pattern of metal lines and second pattern of metal lines. Air gaps are disposed in spaces between the metal lines. Portions of the spaces between the metal lines of the first pattern of metal lines include a conformal layer of insulating material disposed on sidewalls of the metal lines and metallic material that fills the spaces between the metal lines. The first pattern of metal lines comprises a first capacitor electrode, the metallic fill material comprises a second capacitor electrode, and the conformal layer of insulating material comprises an insulating layer of a MIM capacitor structure.

First claim

We claim:

1 . A method, comprising:
forming a dielectric layer on a substrate; forming metal lines in the dielectric layer, wherein the metal lines comprise a first pattern of metal lines and a second pattern of metal lines; etching the dielectric layer to form spaces between the metal lines; forming a capping layer over the dielectric layer to form air gaps in the spaces between the metal lines; patterning the capping layer to expose at least a portion of the first pattern of metal lines and the spaces between the metal lines of the exposed portion of the first pattern of metal lines; forming a conformal layer of insulating material on the exposed portion of the first pattern of metal lines; and filling the exposed spaces between the metal lines of the first pattern of metal lines with a metallic material.

2 . The method of claim 1 , wherein the first pattern of metal lines comprises a first capacitor electrode of a MIM (metal-insulator-metal) capacitor structure, wherein the metallic material filling the exposed spaces between the metal lines of the first pattern of metal lines comprises a second capacitor electrode of the MIM capacitor structure, and wherein the conformal layer of insulating material comprises an insulating layer of the MIM capacitor structure.

3 . The method of claim 2 , wherein the MIM capacitor structure is integrally formed as part of a BEOL (back end of line) structure.

4 . The method of claim 1 , wherein forming the metal lines in the dielectric layer comprises forming damascene copper wiring in an ILD (interlayer dielectric layer) of a BEOL structure.

5 . The method of claim 1 , wherein forming the conformal layer of insulating material on the exposed portion of the first pattern of metal lines comprises depositing a conformal layer of insulating material to cover exposed surfaces of the metal lines of the first pattern of metal lines and exposed surfaces of the dielectric layer within the spaces between the metal lines of the first pattern of metal lines.

6 . The method of claim 1 , wherein the conformal layer of insulating material comprises a high-k dielectric material with a dielectric constant of about 3.9 or greater.

7 . The method of claim 1 , wherein filling the exposed spaces between the metal lines of the first pattern of metal lines with a metallic material comprises filling the exposed spaces with tungsten.

8 . The method of claim 1 , wherein filling the exposed spaces between the metal lines of the first pattern of metal lines with the metallic material comprises:
depositing a layer of metallic material to fill the exposed spaces between the metal lines of the first pattern of metal lines with the metallic material; performing a planarizing process to remove overburden portions of the conformal layer of insulating material and the layer of metallic material disposed on the capping layer, and to form a planarized surface in which surfaces of remaining portions of the capping layer and the layer of metallic material are coplanar.

9 . The method of claim 8 , further comprising:
forming a second dielectric layer on the planarized surface; and forming wiring and vertical contacts in the second dielectric layer, wherein the vertical contacts provide electrical connections between the wiring and the metallic material filled in the exposed spaces between the metal lines of the first pattern of metal lines.

10 . The method of claim 1 , wherein the metal lines comprise aluminum.

11 . The method of claim 1 , wherein the metal lines comprise tungsten.

12 . A method, comprising:
forming a dielectric layer on a substrate; forming metal lines in the dielectric layer, wherein the metal lines comprise a first pattern of metal lines and a second pattern of metal lines, wherein the first pattern of metal lines are commonly connected to each other to form a first capacitor electrode; etching the dielectric layer to form spaces between the metal lines of the first pattern of metal lines, and between the metal lines of the second pattern of metal lines; forming a capping layer over the dielectric layer to form air gaps in the spaces between the metal lines of the first pattern of metal lines, and in the spaces between the metal lines of the second pattern of metal lines; patterning the capping layer to expose the first pattern of metal lines and the spaces between the metal lines of the first pattern of metal lines; depositing a conformal layer of insulating material over the exposed first pattern of metal lines to form a capacitor insulating layer; and depositing a layer of metallic material over the conformal layer of insulating material to fill the exposed spaces between the metal lines of the first pattern of metal lines with a metallic material, wherein the layer of metallic material comprises a second capacitor electrode.

13 . The method of claim 12 , wherein the first capacitor electrode, the second capacitor electrode, and the capacitor insulating layer form a MIM (metal-insulator-metal) capacitor structure.

14 . The method of claim 13 , wherein the MIM capacitor structure is integrally formed as part of a BEOL (back end of line) structure.

15 . The method of claim 12 , wherein forming the metal lines in the dielectric layer comprises forming damascene copper wiring in an ILD (interlayer dielectric layer) of a BEOL structure.

16 . The method of claim 12 , wherein depositing the conformal layer of insulating material over the first pattern of metal lines to form the capacitor insulating layer comprises depositing a conformal layer of insulating material to cover exposed surfaces of the metal lines of the first pattern of metal lines and exposed surfaces of the dielectric layer within the spaces between the metal lines of the first pattern of metal lines.

17 . The method of claim 12 , wherein the conformal layer of insulating material comprises a high-k dielectric material with a dielectric constant of about 3.9 or greater.

18 . The method of claim 12 , wherein depositing the layer of metallic material over the conformal layer of insulating material comprises depositing a layer of tungsten.

19 . The method of claim 12 , further comprising performing a planarizing process to remove overburden portions of the conformal layer of insulating material and the layer of metallic material disposed on the capping layer, and to form a planarized surface in which surfaces of remaining portions of the capping layer and the layer of metallic material are coplanar.

20 . The method of claim 12 , wherein the metal lines comprise one of aluminum and tungsten.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Standaert Theodorus E
• Wang Junli

Classifications

• H10W20/0888

  wherein via-level dielectrics are compositionally different than trench-level dielectrics · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title