Reconstituted interposer semiconductor package

Patent metadata

Field	Value
Publication number	US-2018233440-A1
Application number	US-201815911500-A
Country	US
Kind code	A1
Filing date	Mar 5, 2018
Priority date	May 21, 2014
Publication date	Aug 16, 2018
Grant date	—

Abstract

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

First claim

1 . A reconstituted interposer package comprising:
an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling an integrated circuit mounted on the first surface of the reconstituted die-attach substrate; a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate, wherein singulated surfaces of the molding compound reside along edges of the interposer substrate and the reconstituted die-attach substrate; and external electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.

2 . The reconstituted interposer package of claim 1 , wherein one or more of the reconstituted interposer packages are assembled into one of a baseband microprocessor, a set-top-box microprocessor, a server message block microprocessor, or an encryption/security microprocessor.

3 . The reconstituted semiconductor package of claim 1 , wherein the molding compound covers side walls of the reconstituted die-attach substrate and the interposer substrate.

4 . The reconstituted semiconductor package of claim 1 , wherein neither the reconstituted die-attach substrate nor the interposer substrate are traversed during singulation.

5 . The reconstituted semiconductor package of claim 1 , further comprising an interposer package-on-package.

6 . The reconstituted semiconductor package of claim 1 , wherein a size of the interposer substrate is different from a size of the reconstituted die-attach substrate.

7 . A reconstituted interposer package comprising:
an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling an integrated circuit mounted on the first surface of the reconstituted die-attach substrate; a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate; and electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.

8 . The reconstituted semiconductor package of claim 7 , wherein the molding compound covers side walls of the reconstituted die-attach substrate and the interposer substrate.

9 . The reconstituted semiconductor package of claim 7 , wherein one or more of the reconstituted interposer packages are assembled into one of a baseband microprocessor, a set-top-box microprocessor, a server message block microprocessor, or an encryption/security microprocessor.

10 . The reconstituted semiconductor package of claim 7 , further comprising an interposer package-on-package.

11 . The reconstituted semiconductor package of claim 7 , wherein a size of the interposer substrate is different from a size of the reconstituted die-attach substrate.

12 . A method of forming a semiconductor package, comprising:
forming an array of die-attach substrates; mounting a semiconductor device onto a first surface of each of the die-attach substrates; forming solder ball or conductor post connections to a plurality of interposer substrates; mounting each interposer substrate over a respective semiconductor device; electrically connecting the interposer substrates to the first surface of the respective die-attach substrates, via the solder ball or conductor post connections; filling a molding compound in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages; mounting electrical connections to a second surface of the die-attach substrates; and singulating the array of reconstituted semiconductor packages through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

13 . The method of claim 12 , wherein the array of reconstituted semiconductor packages comprises a gap between each of the die-attach substrates and their respective mounted interposer substrates.

14 . The method of claim 13 , wherein the singulation does not cut through either the die-attach substrates or the mounted interposer substrates.

15 . The reconstituted semiconductor package of claim 13 , wherein the molding compound fills the gaps between each of the die-attach substrates and their respective mounted interposer substrates.

16 . The reconstituted semiconductor package of claim 12 , wherein the singulation cuts through the die-attach substrates.

17 . The reconstituted semiconductor package of claim 12 , wherein the singulation cuts through the interposer substrates.

18 . The method of claim 12 , further comprising:
forming the array of die-attach substrates onto an adhesive tape carrier.

19 . The method of claim 18 , further comprising:
exposing portions of the adhesive tape carrier through a solder mask to form a solder stencil.

20 . The method of claim 19 , further comprising:
forming solder electrical connections within the exposed portions of the solder stencil.

Assignees

• Avago Technologies General Ip

Inventors

• Law Edward
• Zhao Sam Ziqun
• Hu Kunzhong
• Khan Rezaur Rahman

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title