Slew-driven clock tree synthesis

Patent metadata

Field	Value
Publication number	US-10338633-B2
Application number	US-201715621940-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Jun 13, 2016
Publication date	Jul 2, 2019
Grant date	Jul 2, 2019

Abstract

A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.

First claim

The invention claimed is:

1. A system for performing slew-driven clock tree synthesis for selecting a merging point location for a set of existing nodes comprising the steps:
pair selection and cost metric definition considering physical distance between nodes for efficient sink clustering;
slew and skew-aware merging point computation for routing; and
slew and insertion slew-aware net splitting;
wherein pair selection, slew and skew-aware merging point computation, and slew and insertion slew-aware net splitting merge pairs of nodes into a new node and the steps are repeated for pairs from the set of nodes and a set of new nodes until the number of nodes from the set of nodes and new nodes equals one node, wherein the one is the merging point location, wherein the repeating of the steps is an iteration.

2. The system of claim 1 , wherein the pair selection comprises distance-based techniques in which minimum distance pairs of nodes are selected for merging together.

3. The system of claim 2 , wherein the merging pair selection considers all possible pairings of nodes at each iteration.

4. The system of claim 1 , wherein the merging point location is determined to perform routing of a minimum cost pair of nodes.

5. The system of claim 1 , wherein the merging point location is determined within a merging region considering a slew constraint in the same phase.

6. The system of claim 5 , wherein a zero skew merging point location is selected according to the equation (1):

L
i

=

0.5
⁢

C
unit

⁢

L
⁡

(

i
,
j

)

2

+

L
⁡

(

i
,
j

)

⁢

C
j

C
i

+

C
j

+

L
⁡

(

i
,
j

)

⁢

C
unit

+

t
j

-

t
i

R
unit

⁡

(

C
i

+

C
j

+

L
⁡

(

i
,
j

)

⁢

C
unit

)

,

(
1
)

where Li is the merging point location, L(i; j) is the distance between two nodes), Runit and Cunit are a per unit resistance (Ω=μm) and capacitance (fF/μm) of an interconnect between the two nodes, ti and tj are an insertion delay from i and j to their sinks, respectively, and Ci and Cj are the capacitance at the two nodes, respectively.

7. The system of claim 6 , wherein merging point computation comprises a Logic Flow comprising the following:
1: Maxi=max[Dins(i)]
2: Maxj=max[Dins(j)]
3: Mini=min[Dins(i)]+skewconst
4: Min j=min[Dins(i)]+skewconst
5: Compute CS1 by computing LCS1 with equation (1) for ti=Maxi,
tj=Min j
6: Compute CS2 by computing LCS2 with equation (1) for ti=Mini,
tj=Maxj
7: Compute min slew point m by solving equation (4)
S i 2 −(ln(9)× ED ( m,i )) 2 =S j 2 −(ln(9)× ED ( m,j )) 2   (4)

where Si and Sj are target slew values at the two nodes i and j, ED(m,i) and ED (m,j) is an

Assignees

• Univ Drexel
• Stony Brook Univ

Inventors

• Liu Weicheng
• Salman Emre
• Sitik Ahmet Can
• Taskin Baris

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F7/544

  for evaluating functions by calculation {(G06F7/4824 takes precedence)} · CPC title

• G06F30/396

  Clock trees · CPC title