Embedded graphite heat spreader for 3dic

Patent metadata

Field	Value
Publication number	US-2018219001-A1
Application number	US-201815927494-A
Country	US
Kind code	A1
Filing date	Mar 21, 2018
Priority date	Mar 5, 2015
Publication date	Aug 2, 2018
Grant date	—

Abstract

A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

First claim

What is claimed is:

1 . A device, comprising:
a plurality of die positioned in a stack, each die including a chip, electrical interconnects extending through a thickness of the chip to provide an electrical path from a top side of the chip to a bottom side of the chip, and metal features on the bottom side coupled to the electrical interconnects; at least one thermally conducting layer coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack; and a heat sink coupled to the thermally conducting layer.

2 . The device of claim 1 , wherein the thermally conducting layer is a pyrolytic graphite layer.

3 . The device of claim 1 , wherein the chip is a silicon chip.

4 . The device of claim 1 , wherein the metal features are solder balls, solder caps, or pads.

5 . The device of claim 1 , further including an adhesive layer bonding the at least one thermally conducting layer to a die of the plurality of die.

6 . The device of claim 5 , further including an electrically insulating but thermally conducting layer on the at least one thermally conducting layer opposite the adhesive layer.

7 . The device of claim 6 , further including a side electrically insulating but thermally conducting layer extending in the direction of thickness of said dies that contacts each of the electrically insulating but thermally conducting layers and the at least one thermally conducting layer.

8 . The device of claim 7 , further comprising a metal layer adjacent the electrically insulating but thermally conducting layer.

9 . The device of claim 7 , further including a substrate, the substrate including heat paths thermally coupled to the side electrically insulating but thermally conducting layer and the metal layer.

10 . The device of claim 1 , wherein the interconnects form signal posts and thermal posts, the signal posts on the top of each die being electrically isolated from the thermally conducting layer and the thermal posts being directly coupled to the thermally conducting layer.

11 . The device of claim 1 , wherein the thermally conducting layer is a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer.

12 . The device of claim 10 , wherein metal features of electrically conductive composition are connected to a bottom die of the stack to couple the stack to a substrate.

13 . A stacked microelectronic device, comprising:
a plurality of die, each of the die with a thermally conducting sheet on a top side of a silicon chip, and with electrically insulating but thermally conducting material at one or more edges of the thermally conducting sheet; wherein the die are stacked to form a stack such that the thermally conducting sheet of each of one or more of the die is disposed between the die, at least one die's electrically insulating but thermally conducting material electrically insulating the die's thermally conducting sheet from at least one interconnect that electrically connects the die to an overlying die in the stack; a substrate onto which the stack of the plurality of die is mounted; and a heat sink mounted to the stack of the plurality of die opposite the substrate.

14 . The stacked microelectronic device of claim 13 , further comprising an electrically insulating but thermally conducting layer on a side wall of the stacked plurality of die such that the electrically insulating but thermally conducting layer on the side wall contacts each said thermally conducting sheet in the stack;
wherein the electrically insulating but thermally conducting layer on the side wall connects with a heat path through the substrate.

15 . The stacked microelectronic device of claim 14 further including a metal layer over the electrically insulating but thermally conducting layer on the side wall.

16 . The stacked microelectronic device of claim 13 wherein at least one said thermally conducting sheet is a pyrolytic graphite sheet.

17 . A microelectronic device comprising:
a first integrated circuit with circuitry; a first layer over the first integrated circuit, with at least one of properties (i) and (ii) being true with regard to a thermal conductivity of the first layer in at least one lateral direction: (i) the first layer comprises a metal, and said thermal conductivity is at least as high as a thermal conductivity of a layer of such metal in at least one lateral direction; (ii) the first layer comprises carbon, and said thermal conductivity is at least as high as a thermal conductivity of a layer of such carbon in at least one lateral direction; one or more first vias each of which passes through the first layer and exposes a corresponding first region of the circuitry of the first integrated circuit; a second integrated circuit comprising circuitry and attached to the first integrated circuit, at least part of the first layer lying between the first and second integrated circuits, the circuitry of the second integrated circuit being electrically connected to each first region by a corresponding electrical connection reaching the first region through the corresponding first via; and an electrically insulating layer between the first layer and the second integrated circuit.

18 . The microelectronic device of claim 17 further comprising, between the electrically insulating layer and the second integrated circuit, a conductive feature on each first region, each conductive feature being electrically insulated from the first layer by the electrically insulating layer;
wherein the second integrated circuit is attached to each said conductive feature.

19 . The microelectronic device of claim 17 wherein the electrically insulating layer is at least as thermally conducting as diamond-like carbon.

20 . The microelectronic device of claim 17 wherein the electrically insulating layer comprises diamond-like carbon.

Assignees

• Invensas Corp

Inventors

• Gao Guilian
• Woychik Charles G
• Uzoh Cyprian Emeka
• Wang Liang

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title