An apparatus and method for performing a splice operation

Patent metadata

Field	Value
Publication number	US-2018210733-A1
Application number	US-201615745478-A
Country	US
Kind code	A1
Filing date	Jun 15, 2016
Priority date	Jul 31, 2015
Publication date	Jul 26, 2018
Grant date	—

Abstract

An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.

First claim

1 . An apparatus, comprising:
a set of vector registers; one or more control registers; and processing circuitry to execute a sequence of instructions including a splice instruction identifying at least a first vector register and at least one control register, the first vector register storing a first vector of data elements having a vector length, and the at least one control register storing control data identifying, independently of the vector length, one or more data elements occupying sequential data element positions within the first vector of data elements; the processing circuitry being responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register and to output the extracted data elements within a result vector of data elements that also contains data elements from a second vector.

2 . An apparatus as claimed in claim 1 , wherein the processing circuitry is arranged to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector.

3 . An apparatus as claimed in claim 1 , wherein the splice instruction further identifies a second vector register storing the second vector of data elements, and the processing circuitry is responsive to execution of the splice instruction to include, at each data element position in the result vector unoccupied by the extracted data elements, a data element from the second vector of data elements.

4 . An apparatus as claimed in claim 3 , wherein the processing circuitry is arranged to include within the result vector sequential data elements starting from a first end of the second vector of data elements.

5 . An apparatus as claimed claim 1 , wherein:
said one or more control registers comprise at least one predicate register, each predicate register used to store predicate data for each data element position within a vector of data elements; and the at least one control register identified in the splice instruction comprises one of said at least one predicate registers, the processing circuitry being responsive to execution of the splice instruction to determine from the predicate data each data element to be extracted from the first vector.

6 . An apparatus as claimed in claim 5 , wherein the predicate data provides location and length information used to determine the one or more data elements to be extracted from the first vector of data elements.

7 . An apparatus as claimed in claim 6 , wherein the predicate data identifies a first extraction data element position and a last extraction data element position, and the processing circuitry determines, as the data elements to be extracted, a sequence of data elements between the first extraction data element position and the last extraction data element position.

8 . An apparatus as claimed in claim 1 , further comprising:
said one or more control registers comprises one or more scalar registers for storing data values; the at least one control register identified in the splice instruction comprises at least one scalar register, the processing circuitry being responsive to execution of the splice instruction to use the data value in each identified scalar register when determining each data element to be extracted from the first vector.

9 . An apparatus as claimed in claim 8 , wherein the splice instruction identifies first and second scalar registers whose stored data values provide location and length information used to determine the one or more data elements to be extracted from the first vector of data elements.

10 . An apparatus as claimed in claim 9 , wherein the stored data values in the first and second scalar registers identify a first extraction data element position and a last extraction data element position, and the processing circuitry determines, as the data elements to be extracted, a sequence of data elements between the first extraction data element position and the last extraction data element position.

11 . An apparatus as claimed in claim 8 , wherein
said one or more control registers comprise at least one predicate register, each predicate register used to store predicate data for each data element position within a vector of data elements; the at least one control register identified in the splice instruction comprises one of said at least one predicate registers, the processing circuitry being responsive to execution of the splice instruction to determine from the predicate data each data element to be extracted from the first vector; and the at least one control register identified in the splice instruction comprises one of said at least one predicate registers and one of the scalar registers, the data value in the identified scalar register being used in combination with the predicate data in the identified predicate register to determine the one or more data elements to be extracted from the first vector of data elements.

12 . An apparatus as claimed in claim 3 , wherein the first vector register and the second vector register are the same vector register.

13 . An apparatus as claimed in claim 3 , wherein the first vector register is a predicate register used to store predicate data for each data element position within a vector of data elements.

14 . An apparatus as claimed in claim 13 , wherein each data element comprises a single bit.

15 . An apparatus as claimed in claim 1 , wherein the processing circuitry is arranged to execute the splice instruction in each of a plurality of iterations, in each iteration control data in the at least one control register identified by the splice instruction identifying one or more data elements to be extracted from the first vector of data elements that differs to the one or more data elements identified for extraction during a preceding iteration.

16 . An apparatus as claimed in claim 1 , wherein the processing circuitry comprises vector permute circuitry.

17 . An apparatus as claimed in claim 16 , wherein the splice instruction further identifies a second vector register storing the second vector of data elements, and the processing circuitry is responsive to execution of the splice instruction to include, at each data element position in the result vector unoccupied by the extracted data elements, a data element from the second vector of data elements, and, wherein the vector permute circuitry comprises:
first shift circuitry to perform a first shift operation on the first vector of data elements and second shift circuitry to perform a second shift operation on the second vector of data elements; combination circuitry to generate the result vector from the vectors output by the first and second shift circuitry; and analysis circuitry to analyse the control data in the at least one control register in order to determine said one or more data elements to be extracted from the first vector of data elements, and to issue control signals to control the operation of the first and second shift circuitry in dependence on said analysis.

18 . An apparatus as claimed in claim 17 , wherein the vector permute circuitry further comprises:
first mask circuitry to perform a first mask operation on the vector output by the first shift circuitry in order to produce a first masked vector, and second mask circuitry to perform a second mask operation on the vector output by the second shift circuitry in order to produce a second masked vector; the combination circuitry being arranged to generate the result

Assignees

• Advanced Risc Mach Ltd

Inventors

• Stephens Nigel John
• Eapen Jacob
• Eyole Mbou

Classifications

• G06F9/30192 Primary

  according to data descriptor, e.g. dynamic data typing · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30038 Primary

  using a mask · CPC title