Front end circuit

Patent metadata

Field	Value
Publication number	US-2018205345-A1
Application number	US-201815909067-A
Country	US
Kind code	A1
Filing date	Mar 1, 2018
Priority date	May 29, 2015
Publication date	Jul 19, 2018
Grant date	—

Abstract

A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.

First claim

What is claimed is:

1 . A front end circuit, comprising:
a transmission and reception switch; a bypass circuit comprising a first bypass switch and a second bypass switch, connected to the transmission and reception switch, and configured to bypass an input signal to an output terminal based on switching operations of the first bypass switch and second bypass switch; and an amplifier connected in parallel to the bypass circuit, and configured to amplify the input signal, wherein the bypass circuit is connected between the transmission and reception switch and the output terminal.

2 . The front end circuit of claim 1 , wherein the bypass circuit further comprises a reducer connected in series between the first bypass switch and the second bypass switch.

3 . The front end circuit of claim 1 , wherein the transmission and reception switch is configured to maintain an ON state when the front end circuit performs a reception operation.

4 . The front end circuit of claim 1 , wherein the bypass circuit further comprises a reducer connected between the first bypass switch and the second bypass switch, the reducer being configured to reduce the input signal, and one end of the second bypass switch being connected to the output terminal.

5 . The front end circuit of claim 1 , wherein the first bypass switch and the second bypass switch are configured to receive a same switching control signal to perform the switching operations.

6 . The front end circuit of claim 1 , wherein the first bypass switch and the second bypass switch are configured to match either one or both input or output impedance of the bypass circuit to about 50 ohms.

7 . The front end circuit of claim 1 , wherein the amplifier comprises:
a first amplifying switch, one end of which is connected to an input terminal configured to receive the signal; an amplifying part, one end of which is connected to the other end of the first amplifying switch, the amplifying part being configured to amplify the signal; and a second amplifying switch, one end of which is connected to the other end of the amplifying part and the other end of the second amplifying switch being connected to the output terminal.

8 . The front end circuit of claim 1 , wherein the amplifier comprises:
a first amplifying switch, one end of which is connected to an input terminal configured to receive the signal; a first amplifying part, a gate terminal of which is connected to an other end of the first amplifying switch, and a source terminal of the first amplifying part being grounded; a second amplifying part, a source terminal of which is connected to a drain terminal of the first amplifying switch, and a drain terminal of the second amplifying part being connected to the output terminal; and a second amplifying switch, one end of which is connected to an other end of the second amplifying part and the other end of which is connected to the output terminal.

9 . The front end circuit of claim 1 , wherein the bypass switch is serially connected to the transmission and reception switch, and one end of the second bypass switch is connected to the output terminal.

10 . The front end circuit of claim 4 , wherein the reducer comprises:
a first resistor, one end of which is connected to an end of the first bypass switch and the other end of the first resistor being connected to an other end of the second bypass switch; a second resistor, one end of which is connected to the one end of the first resistor and the other end of which is grounded; and a third resistor, one end of which is connected to the other end of the first resistor and the other end of which is grounded.

11 . The front end circuit of claim 10 , wherein each of the first bypass switch and the second bypass switch comprises stacked intercoupled switches.

12 . The front end circuit of claim 10 , wherein the first and second amplifying switches are configured to match input and/or output impedance of the amplifying part to about 50 ohms.

13 . A front end circuit, comprising:
a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; an amplifier connected in parallel to the bypass circuit and configured to amplify the signal; and a transmission and reception switch, a first end of which is connected to an input terminal and a second end of which is connected to the amplifier and the bypass circuit.

14 . The front end circuit of claim 13 , wherein the transmission and reception switch is configured to maintain an ON state in response to the front end circuit performing a reception operation.

Assignees

• Samsung Electro Mech

Inventors

• Kim Sang Hee

Classifications

• H03F1/22 Primary

  by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively · CPC title

• H03F1/303 Primary

  using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title

• H03F2203/7233

  the gated amplifier, switched on or off by putting into parallel or not, by choosing between amplifiers by one or more switch(es), being impedance adapted by switching an adapted passive network · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F2203/7239

  the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es) · CPC title