Structure and method to reduce shorting and process degradation in stt-mram devices

Patent metadata

Field	Value
Publication number	US-2018190901-A1
Application number	US-201815906480-A
Country	US
Kind code	A1
Filing date	Feb 27, 2018
Priority date	Nov 24, 2015
Publication date	Jul 5, 2018
Grant date	—

Abstract

A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

First claim

What is claimed is:

1 . A magnetic random access memory (MRAM) device, comprising:
a magnetic tunnel junction (MTJ) positioned on an electrode, the MTJ comprising a reference layer positioned in contact with the electrode, a tunnel barrier disposed on the reference layer, and a free layer disposed on the tunnel barrier layer; a hard mask disposed on the free layer of the MTJ; and a sacrificial dielectric material disposed on a top surface of the hard mask, a surface of the electrode, and a sidewall of a portion of the MTJ; wherein a portion of a sidewall of the hard mask is substantially free of the sacrificial dielectric material.

2 . The MRAM of claim 1 , further comprising an encapsulating dielectric layer disposed on the sacrificial dielectric material.

3 . The MRAM of claim 2 , wherein the encapsulating dielectric layer is also disposed on exposed sidewalls of the hard mask and MTJ.

4 . The MRAM of claim 1 , wherein the sacrificial dielectric material is disposed directly in contact with a sidewall of the MTJ.

5 . The MRAM of claim 4 , wherein the encapsulating dielectric layer is disposed directly on the sacrificial dielectric material.

6 . The MRAM of claim 2 , wherein the encapsulating layer is disposed directly on exposed sidewalls of the hard mask, and on the sacrificial dielectric material on the MTJ.

7 . The MRAM of claim 1 , wherein a sidewall of the MTJ is substantially free of redeposited metal.

8 . The MRAM of claim 1 , wherein the sacrificial dielectric material is silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or any combination thereof.

9 . The MRAM of claim 1 , wherein the hard mask comprises a conductive material.

10 . The MRAM of claim 9 , wherein the conductive material is tantalum nitride, titanium nitride, or a combination thereof.

11 . A magnetic random access memory (MRAM) device, comprising:
a magnetic tunnel junction (MTJ) positioned on an electrode, the MTJ comprising a reference layer positioned in contact with the electrode, a tunnel barrier disposed on the reference layer, and a free layer disposed on the tunnel barrier layer; and a sacrificial dielectric material disposed on a top surface of the MTJ, a surface of the electrode, and a sidewall of a portion of the MTJ; wherein a portion of a sidewall of the hard mask is substantially free of the sacrificial dielectric material.

12 . The MRAM of claim 11 , further comprising an encapsulating dielectric layer disposed on the sacrificial dielectric material.

13 . The MRAM of claim 12 , wherein the encapsulating dielectric layer is also disposed on exposed sidewalls of the hard mask and MTJ.

14 . The MRAM of claim 11 , wherein the sacrificial dielectric material is disposed directly in contact with a sidewall of the MTJ.

15 . The MRAM of claim 14 , wherein the encapsulating dielectric layer is disposed directly on the sacrificial dielectric material.

16 . The MRAM of claim 12 , wherein the encapsulating layer is disposed directly on exposed sidewalls of the hard mask, and on the sacrificial dielectric material on the MTJ.

17 . The MRAM of claim 11 , wherein a sidewall of the MTJ is substantially free of redeposited metal.

18 . The MRAM of claim 11 , wherein the sacrificial dielectric material is silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or any combination thereof.

19 . The MRAM of claim 11 , further comprising a hard mask on the MTJ.

20 . The MRAM of claim 19 , wherein the hard mask comprises a conductive material.

Assignees

• IBM

Inventors

• Annunziata Anthony J
• Lauer Gen P
• Nowak Janusz J
• O'Sullivan Eugene J

Classifications

• H01L43/08 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10N50/80

  Constructional details · CPC title