Laterally Diffused Metal Oxide Semiconductor with Gate Poly Contact within Source Window

Patent metadata

Field	Value
Publication number	US-2018190814-A1
Application number	US-201615394636-A
Country	US
Kind code	A1
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Jul 5, 2018
Grant date	—

Abstract

An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

First claim

1 . An integrated circuit comprising:
a semiconductor material substrate; a power transistor having at least one transistor finger that lies within the semiconductor material substrate, each transistor finger including: a source region stripe; a drain region stripe substantially parallel to the source region stripe; a channel region stripe located substantially parallel to and between the source region stripe and the drain region stripe; a gate oxide region stripe that overlies the channel region stripe; spaced apart thick oxide islands that overlie the source region stripe; a gate structure that overlies the gate oxide and the thick oxide islands, in which contacts are connected to the gate structure over the plurality of thick oxide islands; and a conductive gate runner connected to the contacts of the gate structure over the plurality of thick oxide islands.

2 . The integrated circuit of claim 1 , in which the gate structure comprises polysilicon.

3 . The integrated circuit of claim 1 , in which the power transistor is a laterally diffused metal oxide semiconductor device having an extension of the gate structure connected to the source region stripe.

4 . The integrated circuit of claim 1 , in which the at least one transistor finger has a linear topology.

5 . The integrated circuit of claim 1 , in which the conductive gate runner is arranged perpendicularly to the source region stripe.

6 . The integrated circuit of claim 1 , further including control circuitry that lies within the semiconductor material substrate with at least one output signal coupled to the gate structure.

7 . An integrated circuit comprising:
a semiconductor material substrate; a power transistor having at least one transistor finger that lies within the semiconductor material substrate, each transistor finger including: a source region stripe; a drain region stripe substantially parallel to the source region stripe; a gate structure that lies between the source region stripe and the drain region stripe, the gate structure having a plurality of extensions that extend over the source region stripe; contacts connected to the extensions of the gate structure over the source region stripes; and a conductive gate runner connected to the contacts of the gate structure over the source region stripe.

8 . The integrated circuit of claim 7 , further including a separate thick oxide island located in the source region stripe below the contacts of each extension of the gate structure.

9 . The integrated circuit of claim 7 , in which the gate structure comprises polysilicon.

10 . The integrated circuit of claim 7 , in which the conductive gate runner is arranged perpendicularly to the source region stripe.

11 . The power transistor of claim 7 , in which the power transistor is a laterally diffused metal oxide semiconductor device having an extended region connected to the drain region stripe.

12 . The integrated circuit of claim 7 , in which the at least one transistor finger has a linear topology.

13 . The integrated circuit of claim 7 , further including control circuitry that lies within the semiconductor material substrate with at least one output signal coupled to the gate structure.

14 . A method for fabricating a power transistor in an integrated circuit, the method comprising:
diffusing a source region stripe into an epitaxial layer of a semiconductor substrate, and a drain region stripe into the epitaxial layer such that a channel region stripe is located substantially parallel to and between the source region stripe and the drain region stripe; growing thick oxide islands that overlie the source region stripe; forming contacts connected to the gate structure over the thick oxide islands; and forming a conductive gate runner that connects to the contacts of the gate structure over the plurality of thick oxide islands.

15 . The method of claim 14 , further including diffusing into the substrate a first well having a first conductivity type into which the source region stripe is diffused, and diffusing into the substrate a second well having a second conductivity type into which the drain region stripe is diffused.

16 . The method of claim 14 , in which the gate structure comprises polysilicon.

17 . The method of claim 15 , in which the power transistor is a laterally diffused metal oxide semiconductor device and in which the second well forms a drift region.

Assignees

• Texas Instruments Inc

Inventors

• Pendharkar Sameer
• Mathur Guru

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/0653

  Electricity · mapped topic

• H01L29/0692

  Electricity · mapped topic

• H01L29/4916

  Electricity · mapped topic

• H01L21/22

  Electricity · mapped topic