Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Patent metadata

Field	Value
Publication number	US-2018174902-A1
Application number	US-201815889120-A
Country	US
Kind code	A1
Filing date	Feb 5, 2018
Priority date	Aug 5, 2013
Publication date	Jun 21, 2018
Grant date	—

Abstract

Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

First claim

I/We claim:

1 . A semiconductor device, comprising:
a substrate; a conductive trace disposed over the substrate, the conductive trace including:
an inner material having a negative coefficient of thermal expansion (CTE), and
an outer material disposed adjacent the inner material, the outer material having a positive CTE.

2 . The semiconductor device of claim 1 , wherein the inner material is a conductive material arranged in a line, and wherein the outer material is adjacent the line.

3 . The semiconductor device of claim 1 , wherein the outer material is disposed on opposing sides of the inner material.

4 . The semiconductor device of claim 1 , wherein the outer material is a conductive material arranged in parallel lines, and wherein the inner material is between the parallel lines.

5 . The semiconductor device of claim 1 wherein the inner material includes Zr(WO 4 ) 2 .

6 . The semiconductor device of claim 1 wherein the inner material includes ZrV 2 O.

7 . The semiconductor device of claim 1 wherein the inner material includes ZrMo 2 O 8 , ZrW 2 O 8 , HfMo 2 O 8 , or HfW 2 O 8 , or a combination thereof.

8 . The semiconductor device of claim 1 wherein the inner material includes Zr 2 (MoO 4 ) 3 , Zr 2 (WO 4 ) 3 , Hf 2 (MoO 4 ) 3 , Hf 2 (WO 4 ) 3 , or a combination thereof.

9 . The semiconductor device of claim 1 wherein the conductive trace is configured so that at a first temperature, the inner material contracts at a same ratio at which the outer material expands.

10 . The semiconductor device of claim 1 wherein the conductive trace is configured so that at a second temperature, the inner material expands at a same ratio at which the outer material contracts.

11 . The semiconductor device of claim 1 wherein the inner and outer materials together have a composite CTE that is less than the positive CTE, but greater than the negative CTE.

12 . The semiconductor device of claim 9 wherein the composite CTE is less than zero.

13 . The semiconductor device of claim 9 wherein the composite CTE is equal to about zero.

14 . A method of manufacturing a semiconductor device, comprising:
disposing an inner material over a substrate, wherein the inner material has a negative coefficient of thermal expansion (CTE); and disposing an outer material over the substrate and adjacent the inner material, wherein the outer material has a positive CTE.

15 . The method of claim 14 wherein the outer material is disposed on opposing sides of the inner material.

16 . The method of claim 14 wherein the outer material is a conductive material arranged in parallel lines, and wherein the inner material is between the parallel lines.

17 . The method of claim 14 wherein the inner material includes Zr(WO 4 ) 2 .

18 . The method of claim 14 wherein the inner material includes ZrV 2 O.

19 . The method of claim 14 wherein the inner material includes ZrMo 2 O 8 , ZrW 2 O 8 , HfMo 2 O 8 , or HfW 2 O 8 , or a combination thereof.

20 . The method of claim 14 wherein the inner material includes Zr 2 (MoO 4 ) 3 , Zr 2 (WO 4 ) 3 , Hf 2 (MoO 4 ) 3 , Hf 2 (WO 4 ) 3 , or a combination thereof.

21 . The method of claim 14 wherein at a first temperature, the inner material contracts at a same ratio at which the outer material expands.

22 . The method of claim 14 wherein at a second temperature, the inner material expands at a same ratio at which the outer material contracts.

23 . The method of claim 14 wherein the inner and outer materials together have a composite CTE that is less than the positive CTE, but greater than the negative CTE.

24 . The method of claim 23 wherein the composite CTE is less than zero.

25 . The method of claim 23 wherein the composite CTE is equal to about zero.

Assignees

• Micron Technology Inc

Inventors

• Li Hongqi
• Jindal Anurag
• Lu Jin
• Ramalingam Shyam

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W70/095

  of vias therein · CPC title