Semiconductor device including a line pattern having threshold switching devices

Patent metadata

Field	Value
Publication number	US-2018166502-A1
Application number	US-201715630169-A
Country	US
Kind code	A1
Filing date	Jun 22, 2017
Priority date	Dec 8, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

Some example embodiments relate to a semiconductor device including a line pattern, the line pattern having threshold switching devices. The semiconductor device includes a line pattern disposed on a semiconductor substrate. The line pattern includes threshold switching devices and switch separation regions. Data storage patterns may overlap the threshold switching devices. Intermediate electrodes may be disposed between the data storage patterns and the threshold switching devices. The line pattern includes an impurity element, and the concentration of the impurity element in the switch separation regions is higher than the concentration of the impurity element in the threshold switching devices.

First claim

1 . A semiconductor device comprising:
a line pattern on a semiconductor substrate and including threshold switching devices and switch separation regions; data storage patterns overlapping the threshold switching devices; and intermediate electrodes between the data storage patterns and the threshold switching devices, the line pattern including an impurity element, and a concentration of the impurity element in the switch separation regions being higher than the concentration of the impurity element in the threshold switching devices.

2 . The semiconductor device of claim 1 , wherein:
the threshold switching devices include an ovonic threshold switch material, and the switch separation regions include the ovonic threshold switch material doped with the impurity element.

3 . The semiconductor device of claim 1 , wherein the data storage patterns include a phase change memory material.

4 . The semiconductor device of claim 1 , wherein the impurity element comprises at least one of nitrogen (N), arsenic (As), silicon (Si), germanium (Ge) or oxygen (O).

5 . The semiconductor device of claim 1 , further comprising:
a first conductive line on the semiconductor substrate and extending in a first direction; and second conductive lines on the semiconductor substrate and extending in a second direction, the second direction being substantially perpendicular to the first direction, wherein,
the line pattern is on the first conductive line and extends in the first direction,
the threshold switching devices included in the line pattern are below the second conductive lines and overlap the second conductive lines, and
the data storage patterns are between the threshold switching devices and the first conductive line.

6 . The semiconductor device of claim 5 , further comprising:
a first electrode between the first conductive line and the data storage patterns; intermediate electrodes between the data storage patterns and the threshold switching devices; and second electrodes between the threshold switching devices and the second conductive lines, wherein,
the first electrode includes a first portion and a second portion opposite the first portion on the first conductive line, and a connection portion contacting the first conductive line and connecting lower regions of the first portion and the second portion, and
the data storage patterns include a first data storage pattern contacting the first portion of the first electrode and a second data storage pattern contacting the second portion of the first electrode.

7 . The semiconductor device of claim 6 , further comprising:
a first spacer pattern, a second spacer pattern, and an insulating pattern on the connection portion of the first electrode, wherein, the first spacer pattern contacts the first portion of the first electrode,
the second spacer pattern contacts the second portion of the first electrode, and
the insulating pattern is between the first spacer pattern and the second spacer pattern.

8 . The semiconductor device of claim 7 , wherein:
a lower surface of the first data storage pattern contacts an upper surface of the first portion of the first electrode and an upper surface of the first spacer pattern, and a lower surface of the second data storage pattern contacts an upper surface of the second portion of the first electrode and an upper surface of the second spacer pattern.

9 . The semiconductor device of claim 6 , further comprising:
buffer patterns between the second electrodes and the threshold switching devices, wherein the buffer patterns include a different material from the second electrodes.

10 . The semiconductor device of claim 1 , further comprising:
a first conductive line on the semiconductor substrate and extending in a first direction; and first electrodes between the first conductive line and the data storage patterns; intermediate electrodes between the data storage patterns and the threshold switching devices; second conductive lines on the semiconductor substrate, extending in a second direction, the second direction being substantially perpendicular to the first direction, and on a level higher than a level of the line pattern; and second electrodes between the threshold switching devices and the second conductive lines, wherein the first electrodes, the data storage patterns and the intermediate electrodes are stacked on the first conductive lines and have lateral surfaces aligned in a vertical direction thereof.

11 . The semiconductor device of claim 1 , further comprising
a first conductive line on the semiconductor substrate and extending in a first direction; and second conductive lines on the semiconductor substrate, extending in a second direction, the second direction being substantially perpendicular to the first direction, and on a level higher than a level of the line pattern, wherein the threshold switching devices of the line pattern are between the first conductive line and the second conductive lines, and the data storage patterns are between the threshold switching devices of the line pattern and the second conductive lines.

12 . A semiconductor device comprising:
first conductive lines on a semiconductor substrate and extending in a first direction; and a lower structure on the first conductive lines, wherein the lower structure includes,
line patterns on the first conductive lines and extending in the first direction;
second conductive lines on a level higher than a level of the line patterns and extending in a second direction, the second direction being substantially perpendicular to the first direction; and
data storage patterns between the first conductive lines and the second conductive lines,
wherein at least one of the line patterns includes threshold switching devices overlapping the second conductive lines, and switch separation regions between the threshold switching devices and having a different impurity concentration than the threshold switching devices.

13 . The semiconductor device of claim 12 , wherein:
a threshold voltage of the switch separation regions is higher than a threshold voltage of the threshold switching devices, or an off-current of the switch separation regions is lower than an off-current of the threshold switching devices.

14 . The semiconductor device of claim 12 , wherein the line patterns include a threshold switch material and a switch separation material, the switch separation material including the threshold switch material doped with an element changing physical properties of the threshold switch material.

15 . The semiconductor device of claim 12 , further comprising:
an upper structure on the lower structure, the upper structure including a rotated structure that is a same structure as the lower structure, in the second direction by 90°, from the first direction, wherein,
the first direction and the second direction are on a same plane, and
the upper structure is electrically connected to the second conductive lines of the lower structure.

16 . A semiconductor device comprising:
a line pattern on a semiconductor substrate and including a plurality of threshold switching devices alternating with a plurality of switch separation regions in a length direction of the line pattern, the line pattern including an impurity element; and data storage patterns overlapping the threshold switching devices; at least one of,
a threshold voltage of the switch separation regions being higher than a threshold voltage of the threshold switching devices; and
an off-current of the switch separ

Assignees

• Samsung Electronics Co Ltd

Inventors

• Terai Masayuki

Classifications

• H01L45/06

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L27/2481 Primary

  Electricity · mapped topic

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title

• H10N70/841

  Electrodes · CPC title