Buried Insulator Regions and Methods of Formation Thereof

Patent metadata

Field	Value
Publication number	US-2018166324-A1
Application number	US-201715833781-A
Country	US
Kind code	A1
Filing date	Dec 6, 2017
Priority date	Dec 13, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes, wherein forming the buried insulation region comprises forming a plurality of openings in a semiconductor substrate, and forming an oxide within the plurality of openings, wherein the forming of the oxide comprises converting regions of the semiconductor substrate between adjacent ones of the plurality of openings into the oxide; forming a semiconductor layer over the buried insulation region at a first side of the substrate; forming device regions in the semiconductor layer; thinning the substrate from a second side of the substrate to expose the buried insulation region; and forming a conductive region on the thinned second side of the substrate.

2 . The method of claim 1 , further comprising removing the buried insulation region to expose a bottom surface of the substrate; and
forming the conductive region under the bottom surface of the substrate.

3 . The method of claim 1 , wherein forming the device regions comprises:
forming a source region having a first conductivity type at the first side; forming a drift region having the first conductivity type under the source region; and forming a well region separating the source region from the drift region, the well region having a second conductivity type opposite to the first conductivity type.

4 . The method of claim 3 , further comprising:
implanting dopants into the bottom surface and activating the implanted dopants to form at least one of a drain region or a back side emitter after selectively removing the buried insulation region.

5 . The method of claim 1 , wherein forming the buried insulation region comprises forming a plurality of balloon shaped regions connected by thinner regions.

6 . The method of claim 1 , wherein forming the buried insulation region comprises:
forming the plurality of openings in the semiconductor substrate by using an isotropic etching process.

7 . The method of claim 6 , wherein forming the plurality of openings comprises:
forming a plurality of first openings using a first anisotropic etching process; forming a passivation layer at sidewalls and bottom surfaces of the plurality of first openings; forming a plurality of second openings in the semiconductor substrate using a second anisotropic etching process, wherein the second anisotropic etching process comprises etching through the passivation layer at the bottom surfaces of the plurality of first openings; and forming the plurality of openings by extending through the plurality of second openings using an isotropic etching process.

8 . The method of claim 1 , wherein forming the semiconductor layer comprises forming a first epitaxial layer.

9 . The method of claim 8 , wherein forming the first epitaxial layer comprises forming an epitaxial overgrowth layer using a lateral epitaxial overgrowth process, wherein the epitaxial overgrowth layer covers the buried insulation region.

10 . The method of claim 9 , further comprising:
forming a second epitaxial layer over the epitaxial overgrowth layer; and forming the device regions in the second epitaxial layer.

11 . The method of claim 10 , wherein the device region comprises a source and a p-body region of a transistor.

12 . The method of claim 1 , wherein forming the semiconductor layer comprises:
depositing a semiconductor fill material; and annealing the semiconductor layer and the substrate.

13 . The method of claim 12 , wherein the semiconductor fill material comprises an amorphous material.

14 . The method of claim 12 , wherein the semiconductor fill material comprises a polysilicon material.

15 . The method of claim 1 , further comprising planarizing the deposited semiconductor fill material.

16 . The method of claim 1 , wherein the semiconductor layer covers the buried insulation region.

17 . A method of fabricating a semiconductor device, the method comprising:
forming a doped region in a substrate; after forming the doped region, forming a plurality of first openings and pillars in a substrate using a first etching process, wherein each of the plurality of first openings is spaced from another one of the plurality of first openings by one of the pillars; forming a plurality of second openings within the plurality of first openings in the substrate using a second etching process; forming a plurality of third openings in the substrate by exposing the plurality of second openings to an isotropic etching process, wherein the plurality of first openings, the plurality of second openings, and the plurality of third openings are formed in the doped region; forming a plurality of oxide regions at the plurality of third openings to form a continuous region; forming a semiconductor layer over the continuous region; and forming a device region of a vertical semiconductor device in the semiconductor layer.

18 . The method of claim 17 , further comprising:
thinning the substrate from a second side of the substrate to expose the continuous region, wherein forming the semiconductor layer comprises forming an epitaxial overgrowth layer from the pillars using a lateral epitaxial overgrowth process; selectively removing the continuous region; and forming a conductive region on the second side of the substrate.

19 . The method of claim 17 , wherein forming the semiconductor layer comprises forming an epitaxial overgrowth layer from the pillars using a lateral epitaxial overgrowth process, wherein the plurality of first openings is arranged in a periodic pattern of rectangles, wherein each of the rectangles in the periodic pattern of rectangles comprises a width and a length, and wherein the length extends from an edge of a die region of the substrate to an opposing edge of the die region of the substrate.

20 . The method of claim 17 , wherein forming the semiconductor layer comprises forming an epitaxial overgrowth layer from the pillars using a lateral epitaxial overgrowth process, wherein an area between each of the plurality of first openings is arranged in a periodic pattern of rectangles, wherein each of the rectangles in the periodic pattern of rectangles comprises a width and a length, and wherein the periodic pattern of rectangles further comprises a plurality of rows of rectangles, wherein each of the rectangles in each of the plurality of rows of rectangles is has a spatial relationship with each of the rectangles in adjacent rows.

21 . The method of claim 17 , wherein forming the semiconductor layer comprises:
forming a layer comprising a semiconductor material over the pillars and the substrate, wherein the layer comprising the semiconductor material fills the plurality of first openings and covers the continuous region; and annealing the layer comprising the semiconductor material and the substrate to form a single crystal layer.

Assignees

• Infineon Technologies Ag

Inventors

• Schaeffer Carsten
• Moser Andreas
• Kuenle Matthias
• Dainese Matteo
• Rupp Roland
• Schulze Hans-Joachim

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/642

  Chemical etching · CPC title