Multi-height finfet device by selective oxidation

Patent metadata

Field	Value
Publication number	US-2018151702-A1
Application number	US-201515576251-A
Country	US
Kind code	A1
Filing date	Jun 27, 2015
Priority date	Jun 27, 2015
Publication date	May 31, 2018
Grant date	—

Abstract

A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.

First claim

What is claimed is:

1 . A method comprising:
forming a non-planar conducting channel of a multi-gate device on a substrate, the channel comprising a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack comprising a dielectric material and a gate electrode.

2 . The method of claim 1 , wherein modifying comprises oxidizing and prior to oxidizing less than an entire portion of the channel, the method comprises forming a layer of a catalyst material on the channel, wherein the catalyst material comprises a material having a property that will enhance oxidation of a material of the channel.

3 . The method of claim 2 , wherein oxidizing the channel comprises subjecting the channel to a temperature less than an oxidation temperature of a material of the channel.

4 . The method of claim 2 , wherein the layer of the catalyst material is formed exclusively at a base of the channel.

5 . The method of claim 2 , wherein the layer of the catalyst material is formed on the channel from the base of the channel to a height less than an apex of the channel.

6 . The method of claim 5 , wherein the layer of the catalyst material is formed on half of the length of the channel.

7 . The method of claim 3 , wherein forming the catalyst layer comprises depositing the catalyst layer on the entire height dimension of the channel, and, after depositing, the method comprises removing the layer of the catalyst material from a portion of the height dimension of the channel.

8 . The method of claim 1 , wherein the channel is disposed between junction regions on the substrate, the method further comprising oxidizing a portion of the substrate beneath the junction regions.

9 . The method of claim 1 , wherein prior to forming of the gate stack, the method comprises introducing a dielectric material adjacent to the channel to a height equivalent to the oxidized portion of the channel.

10 . A method comprising:
forming a non-planar conducting channel of a multi-gate device on a substrate; oxidizing a portion of the channel, the portion oxidized defined by a height dimension of the channel measured from a surface of the substrate that is less than an overall height dimension of the channel; and forming a gate stack on the channel, the gate stack comprising a dielectric material and a gate electrode.

11 . The method of claim 10 , wherein prior to oxidizing less than an entire portion of the channel, the method comprises forming a layer of a catalyst material on the channel, wherein the catalyst material comprises a material having a property that will enhance oxidation of a material of the channel.

12 . The method of claim 11 , wherein oxidizing the channel comprises subjecting the channel to a temperature less than an oxidation temperature of a material of the channel.

13 . The method of claim 11 , wherein forming the layer of the catalyst material on the channel comprises depositing the layer of the catalyst material on an entire portion of the channel and prior to oxidizing, the method further comprising removing a portion of the layer of the catalyst material.

14 . The method of claim 13 , wherein removing a portion of the layer of the catalyst material comprises removing the layer from at least one half of the overall height dimension of the channel.

15 . The method of claim 10 , wherein the channel is disposed between junction regions on the substrate, the method further comprising oxidizing a portion of the substrate beneath the junction regions.

16 . The method of claim 10 , wherein prior to forming the gate stack, the method comprises introducing a dielectric material adjacent to the channel to a height equivalent to the oxidized portion of the channel.

17 . An apparatus comprising:
a non-planar multi-gate device on a substrate comprising a channel comprising a height dimension defining a conducting portion and a modified portion and a gate stack disposed on the channel, the gate stack comprising a dielectric material and a gate electrode.

18 . The apparatus of claim 17 , wherein the gate stack is disposed exclusively on the conducting portion of the channel.

19 . The apparatus of claim 17 , wherein the modified portion of the channel is disposed between the substrate and the conducting portion of the channel.

20 . The apparatus of claim 17 , wherein the multi-gate device is a first multi-gate device, the apparatus further comprising a second multi-gate device comprising a channel comprising a conducting portion having a height dimension greater than a height dimension of the conducting portion of the first multi-gate device.

21 . The apparatus of claim 17 , wherein the modified portion of the channel is oxidized.

22 . The apparatus of claim 17 , wherein the multi-gate device further comprises a junction region on each of opposite sides of the channel and a region beneath the junction region is oxidized.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Bhimarasetti Gopinath
• Rios Rafael
• Kavalieros Jack T
• Ghani Tahir
• Murthy Anand S
• Mehandru Rishabh

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title