IGBT Die Structure With Auxiliary P Well Terminal

Patent metadata

Field	Value
Publication number	US-2018145162-A1
Application number	US-201815876184-A
Country	US
Kind code	A1
Filing date	Jan 21, 2018
Priority date	Oct 26, 2012
Publication date	May 24, 2018
Grant date	—

Abstract

An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce V CE(SAT) , current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.

First claim

1 - 8 . (canceled)

9 . A method of manufacture comprising:
(a) forming an P type body region that extends into an N type drift layer, wherein the N type drift layer is disposed over a P type substrate layer; (b) forming an auxiliary P type well region that extends into the N type drift layer, wherein the auxiliary P type well region and the P type body region are separated from one another by an amount of the N type drift layer; (c) forming an N type source region that extends into the P type body region; (d) forming a gate; (e) forming a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N type source region; (f) forming a second metal terminal, wherein the second metal terminal is coupled to the gate; (g) forming a third metal terminal, wherein the third metal terminal is coupled to the auxiliary P type well region; and (h) forming a fourth metal terminal that is coupled to the P type substrate layer, wherein the P type substrate layer, the N type drift layer, the P type body region, the auxiliary P type well region, the N type source region, the first metal terminal, the second metal terminal, the third metal terminal, and the fourth metal terminal are all parts of an Insulated Gate Bipolar Transistor (IGBT) die structure.

10 . The method of manufacture of claim 9 , further comprising:
(i) packaging the IGBT die structure in a package such that the first metal terminal of the IGBT die structure is coupled to a first terminal of the package, such that the second metal terminal of the IGBT die structure is coupled to a second terminal of the package, such that the third metal terminal of the IGBT die structure is coupled to a third terminal of the package, and such that the fourth metal terminal of the IGBT die structure is coupled to a fourth terminal of the package.

11 . The method of manufacture of claim 9 , further comprising:
(i) packaging the IGBT die structure in a package along with a current injection/extraction circuit.

12 . The method of manufacture of claim 11 , wherein the packaging of (i) results in: 1) the first metal terminal of the IGBT die structure being coupled to a first terminal of the current injection/extraction circuit, 2) the third metal terminal of the IGBT die structure being coupled to a second terminal of the current injection/extraction circuit, 3) a first terminal of the package being coupled to a third terminal of the current injection/extraction circuit, 4) a second terminal of the package being coupled to the second terminal of the IGBT die structure, and 5) the fourth metal terminal of the IGBT die structure being coupled to a third terminal of the package.

13 . The method of manufacture of claim 9 , wherein the IGBT die structure has a substantially planar upper semiconductor surface, wherein the P type body region extends from the substantially planar upper semiconductor surface and into the N type drift layer, wherein the N type source region extends from the substantially planar upper semiconductor surface and into the P type body region, and wherein the auxiliary P type well region extends from the substantially planar upper semiconductor surface and into the N type drift layer.

14 . A method of turning on an Insulated Gate Bipolar Transistor (IGBT) of an IGBT die structure, wherein the IGBT die structure comprises an IGBT, wherein the IGBT die structure comprises a P type body region that extends into an N type drift layer and also comprises an auxiliary P type well region that extends into the N type drift layer, wherein the IGBT die structure further comprises an N type source region that extends into the P type body region, wherein a first metal terminal of the IGBT die structure is coupled to the N type source region and to the P type body region, wherein a second metal terminal of the IGBT die structure is coupled to a gate, wherein a third metal terminal of the IGBT die structure is coupled to the auxiliary P type well region, and wherein a fourth metal terminal of the IGBT die structure is coupled to a collector of the IGBT, the method comprising:
during a turn on time TON of the IGBT injecting a current into the third metal terminal of the IGBT die structure such that the injected current flows through the third metal terminal and through an auxiliary P type well and into the N type drift layer thereby increasing a concentration of charge carriers in the N type drift layer.

15 . The method of claim 14 , wherein after the turn on time TON the IGBT operates in a forward conduction mode for an amount of time until a turn off time TOFF of the IGBT, the method further comprising:
maintaining a positive voltage on the third terminal with respect to the first terminal throughout the amount of time that the IGBT is operating in the forward conduction mode.

16 . The method of claim 14 , wherein after the turn on time TON the IGBT is turned off in a turn off time TOFF, the method further comprising:
during the turn off time TOFF extracting a current out of the IGBT die structure through the third metal terminal such that a concentration of charge carriers in the N type drift layer is decreased due to a current flow from the N type drift layer, through the auxiliary P type well region, and out of the IGBT die structure via the third metal terminal.

17 - 20 . (canceled)

21 . A method comprising:
(a) injecting charge carriers from an auxiliary P type well region of an Insulated Gate Bipolar Transistor (IGBT) into an N type layer of the IGBT during a turn on time of the IGBT, wherein the IGBT is part of an IGBT die structure that has a terminal coupled to the auxiliary P type well region of the IGBT.

22 . The method of claim 21 , wherein the N type layer is an N− type drift layer.

23 . The method of claim 21 , wherein the IGBT die structure has four terminals, wherein a first terminal of the IGBT die structure is an emitter terminal, wherein a second terminal of the IGBT die structure is a gate terminal, wherein a third terminal of the IGBT die structure is a charge carrier injection/extraction terminal that is the terminal coupled to the auxiliary P type well region of the IGBT, and wherein a fourth terminal of the IGBT die structure is a collector terminal.

24 . The method of claim 21 , wherein during turn on of the IGBT an emitter current flows through an emitter terminal of the IGBT die structure, and wherein during turn on of the IGBT the emitter current changes by approximately twice in magnitude as compared to a change in auxiliary current flowing through the terminal coupled to the auxiliary P type well region of the IGBT.

25 . The method of claim 21 , further comprising:
(b) extracting charge carriers from the N type layer of the IGBT into the auxiliary P type well region of the IGBT during a turn off time of the IGBT.

26 . The method of claim 25 , wherein during turn off of the IGBT an emitter current flows through an emitter terminal of the IGBT die structure, and wherein during turn off of the IGBT the emitter current changes by approximately twice in magnitude as compared to a change in auxiliary current flowing through the terminal coupled to the auxiliary P type well region of the IGBT.

27 . The method of claim 21 , wherein the IGBT die structure is part of an IGBT assembly having an emitter transformer lead, a collector lead, and a gate lead, wherein the IGBT assembly is overmolded with an encapsulant to form a packaged device, and wherein the emitter transformer lead, the collector lead, and the gate lead are the only three metal leads that extend ou

Assignees

• Ixys Corp

Inventors

• Seok Kyoung Wook

Classifications

• H10W90/758

  between a chip and a stacked discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title