Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-2018136554-A1
Application number	US-201715606170-A
Country	US
Kind code	A1
Filing date	May 26, 2017
Priority date	Nov 16, 2016
Publication date	May 17, 2018
Grant date	—

Abstract

A method for fabricating a semiconductor device includes forming a pellicle including an amorphous carbon layer, attaching the pellicle onto a reticle, and forming a photoresist pattern by utilizing EUV light transmitted through the pellicle and reflected by the reticle. The forming the pellicle includes forming a first dielectric layer on a first side of the substrate, forming the amorphous carbon layer on the first dielectric layer, forming a second dielectric layer on a second side of the substrate opposite to the first side of the substrate, etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and forming a support including the second region of the substrate and the remaining part of the first dielectric layer. The forming the support includes etching the first region of the substrate and the first dielectric layer on the first region.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor device, the method comprising:
forming a pellicle including an amorphous carbon layer, the forming the pellicle including,
forming a first dielectric layer on a first side of a substrate that includes a first region and second regions at both sides of the first region,
forming the amorphous carbon layer on the first dielectric layer,
forming a second dielectric layer on a second side of the substrate opposite the first side of the substrate,
etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and
etching the first region of the substrate and the first dielectric layer on the first region of the substrate using the mask pattern to form a support including the second region of the substrate and a remaining part of the first dielectric layer;
attaching the pellicle onto a reticle; and forming a photoresist pattern using extreme ultraviolet (EUV) light, the forming the photoresist pattern including transmitting the EUV light through the pellicle and reflecting the EUV light using the reticle.

2 . The method of claim 1 , wherein the etching the first region of the substrate and the first dielectric layer on the first region of the substrate using the mask pattern to form the support includes:
wet-etching the first region of the substrate with KOH using the mask pattern, and wet-etching or vapor-etching the first dielectric layer on the first region of the substrate with a buffered oxide etch (BOE) process or hydrogen fluoride (HF).

3 . The method of claim 2 , wherein
the first dielectric layer includes silicon oxide, and the second dielectric layer includes silicon nitride.

4 . The method of claim 1 , wherein the etching the first region of the substrate and the first dielectric layer on the first region of the substrate using the mask pattern to form the support includes:
anisotropically etching the first region of the substrate using the mask pattern, and isotropically etching the first dielectric layer on the first region of the substrate.

5 . The method of claim 4 , wherein an interval between the second regions of the substrate becomes smaller as a distance from the first dielectric layer decreases.

6 . The method of claim 1 , further comprising:
forming a protective layer that covers the amorphous carbon layer after the forming the second dielectric layer on the second side of the substrate.

7 . The method of claim 6 , wherein the protective layer includes silicon oxide.

8 . The method of claim 1 , wherein the attaching the pellicle onto the reticle includes attaching the pellicle onto the reticle using a fixing part installed in the reticle.

9 . The method of claim 1 , wherein the etching the first region of the substrate and the first dielectric layer on the first region of the substrate using the mask pattern to form the support further includes removing the mask pattern after etching the first region of the substrate and the first dielectric layer formed on the first region of the substrate, and forming an adhesive layer on the remaining part of the first dielectric layer.

10 . The method of claim 1 , wherein the etching the first region of the substrate and the first dielectric layer on the first region of the substrate using the mask pattern to form the support further includes forming an adhesive layer on the mask pattern.

11 . A method for fabricating a semiconductor device, the method comprising:
forming a pellicle including an amorphous carbon layer, the forming the pellicle including,
forming a first silicon oxide layer on a first side of a silicon substrate, forming the amorphous carbon layer on the first silicon oxide layer,
forming a silicon nitride layer on a second side of the silicon substrate opposite the first side of the silicon substrate, forming a second silicon oxide layer that covers the amorphous carbon layer,
forming a second photoresist pattern on the silicon nitride layer, dry-etching the silicon nitride layer using the second photoresist pattern to form a mask pattern,
wet-etching the silicon substrate and the first silicon oxide layer using the mask pattern to form a support including a remaining portion of the silicon substrate and a remaining portion of the first silicon oxide layer, and
removing the second silicon oxide layer;
attaching the pellicle onto a reticle; and forming a first photoresist pattern using extreme ultraviolet (EUV) light, the forming the first photoresist pattern including transmitting the EUV light through the pellicle and reflecting the EUV light using the reticle.

12 . The method of claim 11 , wherein wet-etching the silicon substrate and the first silicon oxide layer using the mask pattern to form the support includes
wet-etching the silicon substrate with KOH using the mask pattern, and wet-etching or vapor-etching the first silicon oxide layer with a buffered oxide etch (BOE) process or hydrogen fluoride (HF).

13 . The method of claim 11 , wherein a width of the silicon substrate in a part of the support increases toward the first silicon oxide layer.

14 . The method of claim 11 , wherein the forming the amorphous carbon layer on the first silicon oxide layer includes one of plasma-enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a thermal chemical vapor deposition (thermal-CVD) process.

15 . The method of claim 11 , wherein the amorphous carbon layer includes a sp 2 carbon bond and a sp 3 carbon bond.

16 . A method for fabricating a pellicle, the method comprising
forming a protective layer over an amorphous carbon layer of a stacked structure, the stacked structure including the amorphous carbon layer on a first surface of a substrate and a first dielectric layer between the amorphous carbon layer and the substrate, the amorphous carbon layer covering a first region and a second region of the substrate; and removing the first region of the substrate such that the amorphous carbon layer is connected to a remaining portion of the substrate that includes a second region of the substrate.

17 . A method of fabricating a mask assembly, comprising:
forming the pellicle using the method of claim 16 ; attaching a reticle to the pellicle.

18 . A method of fabricating a semiconductor device, comprising:
forming the pellicle using the method of claim 16 ; attaching a reticle to the pellicle; and forming a photoresist pattern using extreme ultraviolet (EUV) light, the forming the photoresist pattern including transmitting the EUV light through the pellicle and reflecting the EUV light using the reticle.

19 . The method of claim 16 , further comprising:
forming the amorphous carbon layer on the first dielectric layer before the forming the protective layer over the amorphous carbon layer of the stacked structure, wherein the forming the amorphous carbon layer includes one of PECVD process, a PVD process, an ALD process, and a thermal-CVD process, the amorphous carbon layer includes a sp 2 carbon bond and a sp 3 carbon bond, and the forming the amorphous carbon layer on the first dielectric layer is performed at a temperature in a range of 400° C. to 500° C.

20 . The method of claim 16 , further comprising:
forming a support, wherein
the forming the support includes etching a portion of the first dielectric layer exposed by the second region of the substrate,
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Assignees

• Samsung Electronics Co Ltd
• Research & Business Found Sungkyunkwan Univ

Inventors

• Yoo Ji Beom
• Kwon Sung Won
• Shin Dong Wook
• Kim Mun Ja
• Kim Jin Su
• Jeon Hwan Chul

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• G03F1/62 Primary

  Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof · CPC title

• H01L21/0274

  Electricity · mapped topic

• G03F1/80

  Etching · CPC title

• G03F7/2004

  characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light · CPC title