Clock synchronizing

Patent metadata

Field	Value
Publication number	US-2018123773-A1
Application number	US-201715798806-A
Country	US
Kind code	A1
Filing date	Oct 31, 2017
Priority date	Nov 1, 2016
Publication date	May 3, 2018
Grant date	—

Abstract

Methods, systems, and machine-readable storage mediums for clock synchronizing among detectors in a clock synchronizing configuration are provided. An example clock synchronizing method includes: providing a clock of a preset frequency in each of N modules to be synchronized, coupling every two adjacent modules of the modules by a transmission line of the same length, N being an odd number, selecting two different modules from the modules as two reference modules respectively, controlling each of the reference modules to transmit a synchronizing signal to the other modules, determining a clock error between every two modules having the same transmission distance from the reference module according to a moment of the synchronizing signal reaching each of the other modules, selecting a calibrating module from the modules, and implementing clock synchronization between each of the modules and the calibrating module according to the respective clock errors associated with the two reference modules.

First claim

1 . A clock synchronizing method comprising:
coupling every two adjacent modules of a plurality of modules by a respective transmission line, the respective transmission lines having a same length, each module having a respective clock of a preset frequency to be synchronized, wherein a number of the plurality of modules N is an odd number; selecting two different modules from the plurality of modules as two reference modules, respectively; for each of the reference modules,
controlling the reference module to transmit a respective synchronizing signal simultaneously in a clockwise direction and an anticlockwise direction via the respective transmission lines until modules other than the reference module in the plurality of modules respectively receive the synchronizing signal once;
determining, for every two modules of the other modules that have a same transmission distance from the reference module, a respective clock error between the two modules based on moments of the synchronizing signal reaching the two modules;
selecting a calibrating module from the plurality of modules; and implementing clock synchronization between each of the plurality of modules and the calibrating module according to the determined respective clock errors for the two reference modules.

2 . The method of claim 1 , wherein a clock synchronization configuration comprises N−1 modules of the plurality of modules, and
wherein the method further comprises:
adding an additional module to the N−1 modules to obtain the N modules, the additional module being provided with a clock of the preset frequency to be synchronized.

3 . The method of claim 1 , wherein determining the respective clock error between the two modules based on moments of the synchronizing signal reaching the two modules comprises:
for each of the two modules, measuring a respective time interval between an edge of a local clock cycle during which the synchronizing signal reaches the module and the moment of the synchronizing signal reaching the module; and determining the clock error between the two modules based on the measured respective time intervals.

4 . The method of claim 3 , wherein measuring the respective time interval comprises:
using at least one of a Time-to-Digital Converter (TDC) or a delay chain in Field-Programmable Gate Array (FPGA) in the module.

5 . The method of claim 3 , wherein measuring the respective time interval comprises:
measuring the respective time interval between an occurrence moment of the edge of the local clock cycle during which the synchronizing signal reaches the module and the moment of the synchronizing signal reaching the module, the edge comprising one of a rising edge and a falling edge.

6 . The method of claim 1 , wherein implementing clock synchronization between each of the plurality of modules and the calibrating module comprises:
acquiring at least one clock error associating the module with the calibrating module from the determined respective clock errors for the reference modules; determining a second clock error between the module and the calibrating module according to the acquired at least one clock error; and implementing the clock synchronization between the module and the calibrating module by calibrating the clock of the module with the second clock error.

7 . The method of claim 6 , wherein calibrating the clock of the module with the second clock error comprises:
delaying the clock of the module with the determined second clock error.

8 . The method of claim 6 , wherein acquiring the at least one clock error associating the module with the calibrating module comprises:
obtaining, from the determined respective clock errors for the reference modules, a first reference clock error associated with the module and a particular module; obtaining a second reference clock error associated with the particular module and the calibration module; and determining the second clock error between the module and the calibrating module based on the obtained first reference clock error and second reference clock error.

9 . The method of claim 8 , wherein obtaining the second reference clock error associated with the particular module and the calibration module comprises one of:
obtaining the second reference clock error associated with the particular module and the calibration module from the determined respective clock errors for the reference modules, and obtaining, from the determined respective clock errors for the reference modules, a third reference clock error associated with the particular module and a second particular module and a fourth reference clock error associated with the second particular module and the calibration module and determining the second reference clock error based on the third reference clock error and the fourth reference clock error.

10 . A clock synchronizing apparatus for a clock synchronizing configuration, the apparatus comprising:
a processor; and a non-transitory machine-readable storage medium, wherein, by invoking and executing machine-executable instructions corresponding to a clock synchronizing control logic stored on the machine-readable storage medium, the processor is caused to:
select two different modules from N modules as two reference modules respectively, each of the N modules being provided a clock of a preset frequency to be synchronized, every two adjacent modules of the N modules being coupled by a transmission line of the same length, N being an odd number;
control each of the reference modules to output a synchronizing signal in a way that the synchronizing signal is simultaneously transmitted in a clockwise direction and an anticlockwise direction until modules other than the reference module in the N modules respectively receive the synchronizing signal once;
determine a clock error between every two modules that have the same transmission distance from the reference module according to a moment of the synchronizing signal reaching each of the other modules;
select a calibrating module from the N modules; and
implement clock synchronization between each of the N modules and the calibrating module according to the respective clock errors associated with each of the two reference modules.

11 . The apparatus of claim 10 , wherein the clock synchronization configuration comprises N−1 modules of the N modules, and
wherein the processor is caused to add an additional module to the clock synchronizing configuration to obtain the N modules, the additional module being provided with a clock of the preset frequency.

12 . The apparatus of claim 10 , wherein, when determining the clock error between every two modules that have the same transmission distance from the reference module according to the moment of the synchronizing signal reaching each of the other modules, the machine-executable instructions cause the processor to:
for each of the other modules, measure a time interval between an edge of a local clock cycle during which the synchronizing signal reaches the module and the moment of the synchronizing signal reaching the module; and determine the clock error between every two modules that have the same transmission distance from the reference module according to the respective time intervals.

13 . The apparatus of claim 12 , wherein, when measuring the time interval between the edge of the local clock cycle during which the synchronizing signal reaches the module and the moment of the synchronizing signal reaching the module, the machine-executable instructions cause the processor to:
measure, with a Time-to-Digital Converter (TDC), the time interval between the

Assignees

• Shenyang Neusoft Medical Sys

Inventors

• Cui Gai
• Yang Long
• Zhang Jun
• Ning Peng
• Zhang Zhenguo

Classifications

• H04L67/12

  specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks · CPC title

• A61B6/037

  Emission tomography · CPC title

• G01T1/2985

  In depth localisation, e.g. using positron emitters; Tomographic imaging (longitudinal and transverse section imaging; apparatus for radiation diagnosis sequentially in different planes, steroscopic radiation diagnosis); (using external radiation sources A61B6/02) · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title