Time-to-digital converter

Patent metadata

Field	Value
Publication number	US-9989928-B2
Application number	US-201715667114-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Feb 3, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A time-to-digital converter includes: an input for receiving a time-domain input signal; an output for providing a digital output signal; a time register coupled to the input and to a first node; a time quantizer coupled to the time register for providing the digital output signal at the output; and a digital-to-time converter coupled to the output for providing a feed-back signal at the first node.

First claim

What is claimed is:

1. A time-to-digital converter comprising:
an input for receiving a time-domain input signal;
an output for providing a digital output signal;
a time register coupled to the input and to a first node;
a time quantizer coupled to the time register for providing the digital output signal at the output; and
a digital-to-time converter coupled to the output for providing a feedback signal at the first node, wherein the digital-to-time converter is further coupled to the time register for delaying an output signal of the time register in response to the digital output signal.

2. The time-to-digital converter, of claim 1 , wherein the digital output signal is an oversampled representation of the time-domain input signal.

3. The time-to-digital converter of claim 1 , wherein the feedback signal is a quantization error signal.

4. The time-to-digital converter of claim 1 , wherein the time register is configured to combine the time-domain input signal with the feedback signal to produce a modified time-domain input signal.

5. The time-to-digital converter of claim 4 , wherein the combination is a subtraction.

6. The time-to-digital converter of claim 4 , wherein the time register is configured to delay the modified time-domain input signal by at least one cycle of a sampling clock.

7. The time-to-digital converter of claim 1 , wherein the time-domain input signal comprises a pair of two input signals.

8. The time-to-digital converter of claim 7 , wherein the two input signals comprise a first digital clock and a second digital clock.

9. The time-to-digital converter of claim 8 , wherein a value of the time-domain input signal corresponds to a time difference between a transition of the first digital clock and a transition of the second digital clock.

10. The time-to-digital converter of claim 1 , wherein the time quantizer is configured to produce 1.5 bits.

11. The time-to-digital converter of claim 1 , wherein a resolution of the time quantizer is 1.5 bits.

12. The time-to-digital converter of claim 1 , comprising a plurality of time quantizers arranged to operate in pipeline.

13. A high-order time-to-digital converter comprising:
an input for receiving a time-domain input signal;
a plurality of first-order time-to-digital converters, a first one thereof coupled to the input;
a combiner coupled to the plurality of first-order time-to-digital converters for producing a digital output signal;
wherein the first one of the plurality of first-order time-to-digital converters is configured to produce a time quantization error signal that is fed to the next one of the plurality of first-order time-to-digital converters;
wherein each of the plurality of first-order time-digital converters comprises:
a respective input for receiving a respective time-domain input signal;
a respective output for providing a respective digital output signal;
a respective time register coupled to the respective input and to a respective first node;
a respective time quantizer coupled to the respective time register for providing the respective digital output signal at the respective output; and
a respective digital-to-time converter coupled to the respective output for providing a respective feedback signal at the respective first node.

14. The high-order time-to-digital converter of claim 13 , wherein the digital output signal is a digital representation of the time-domain input signal including a noise-shaped quantization error.

15. The high-order time-to-digital converter of claim 13 , wherein the respective digital-to-time converter is further coupled to the respective time register for delaying a respective output signal of the respective time register in response to the respective digital output signal.

16. A time-to-digital converter comprising:
an input for receiving a time-domain input signal;
an output for providing a digital output signal;
a time register coupled to the input and to a first node;
a plurality of time quantizers arranged to operate in pipeline, wherein the plurality of time quantizers comprise a time quantizer coupled to the time register for providing the digital output signal at the output; and
a digital-to-time converter coupled to the output for providing a feedback signal at the first node.

Assignees

• Huawei Tech Co Ltd

Inventors

• Wu Ying
• Staszewski Robert Bogdan
• Mao Yihong

Classifications

• H03M3/414

  having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title