Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-2018108779-A1
Application number	US-201715844863-A
Country	US
Kind code	A1
Filing date	Dec 18, 2017
Priority date	May 26, 2015
Publication date	Apr 19, 2018
Grant date	—

Abstract

A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, comprising:
forming a fin pattern defined by a device isolation layer on a substrate, the fin pattern comprising a gate fin region and a source/drain fin region; and performing a trimming process on the source/drain fin region selectively to reduce a width of the source/drain fin region, wherein the fin pattern extends in a first direction, and wherein, when measured in a second direction crossing the first direction, the width of the source/drain fin region at a height is different from a width of the gate fin region at the height.

2 . The method of claim 1 , wherein the width of the source/drain fin region at the height is less than the width of the gate fin region at the height.

3 . The method of claim 1 , wherein the width of the source/drain fin region becomes gradually wider toward the substrate.

4 . The method of claim 1 , wherein the source/drain fin region has a lower portion and an upper portion,
wherein the upper portion is disposed at a level higher than the lower portion, and wherein the lower portion has a width that increases toward the substrate at a ratio different from the upper portion.

5 . The method of claim 1 , wherein the source/drain fin region has a lower portion and an upper portion,
wherein the upper portion is disposed at a level higher than the lower portion, and wherein the lower portion has a width that increases toward the substrate at a higher change rate than the upper portion.

6 . The method of claim 1 , wherein the source/drain fin region is formed to have a concave sidewall.

7 . The method of claim 1 , wherein the source/drain fin region comprises a portion having a width the same as the width of the gate fin region.

8 . The method of claim 1 , further comprising:
an active region below the source/drain fin region, wherein the source/drain fin region comprises a portion having the same width as the width of the active region.

9 . A method of fabricating a semiconductor device, comprising:
forming an insulating layer in a substrate; etching an upper portion of the insulating layer to form a fin pattern comprising a gate fin region and a source/drain fin region; forming a sacrificial pattern on the gate fin region, the sacrificial pattern exposing the source/drain fin region; and performing a trimming process on the source/drain fin region selectively to reduce a width of the source/drain fin region, wherein the fin pattern extends in a first direction, and wherein, when measured in a second direction crossing the first direction, the width of the source/drain fin region at a height is different from a width of the gate fin region at the height.

10 . The method of claim 9 , wherein the trimming process comprises a wet etching process or a cleaning process.

11 . The method of claim 10 , wherein the source/drain fin region is formed to have a concave sidewall by performing the wet etching process or the cleaning process.

12 . The method of claim 9 , wherein a lower portion of the source/drain fin region has a width that increases toward the substrate at a higher change rate than an upper portion of the source/drain fin region.

13 . The method of claim 9 , wherein the trimming process comprises a dry etching process.

14 . The method of claim 9 , further comprising:
before performing the trimming process, forming spacers on opposite sidewalls of the sacrificial pattern, respectively.

15 . The method of claim 9 , further comprising:
forming a source/drain portion using an epitaxial growth process, in which the source/drain fin region is used as a seed layer.

16 . A method of fabricating a semiconductor device, comprising:
forming a fin pattern defined by a device isolation layer on a substrate; and performing a trimming process on a portion of the fin pattern selectively to form a source/drain fin region, the source/drain fin region formed to have a concave sidewall, wherein the fin pattern extends in a first direction, wherein, when measured in a second direction crossing the first direction, a width of the source/drain fin region at a height is different from a width of another portion of the fin pattern at the height.

17 . The method of claim 16 , wherein the concave sidewall has at least two portions having slopes different from each other.

18 . The method of claim 16 , wherein the concave sidewall has an upper sidewall and a lower sidewall,
wherein the lower sidewall is disposed at a low level than the upper sidewall, wherein a slope of the upper sidewall is larger than a slope of the lower sidewall, and wherein the slopes are with respect to an upper surface of the substrate.

19 . The method of claim 16 , wherein the width of the source/drain fin region becomes gradually wider toward the substrate.

20 . The method of claim 16 , wherein the source/drain fin region has a lower portion and an upper portion,
wherein the upper portion is disposed at a level higher than the lower portion, and wherein the lower portion has a width that increases toward the substrate at a higher change rate than the upper portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Sujin
• Kim Jinbum
• Moon Kang Hun
• Lee Kwan Heum
• Lee Byeongchan
• Lee Choeun
• Xu Yang

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6211 Primary

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H01L29/7851 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic